SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF

• US 20170148520A1
• Filed: 04/15/2016
• Published: 05/25/2017
• Est. Priority Date: 11/23/2015
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: OH, Hae Soon
• Granted Patent: US 10,121,545 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

There are provided an operating method of a semiconductor memory device including a plurality of memory cells each having one of “n” number of program statuses as a target program status, the operating method comprising: setting a first group of the memory cells, which have a first group of the program statuses as the target program status, to a program permit mode; setting a second group of the memory cells, which have a second group of the program statuses as the target program status, to a program inhibit mode; performing a program operation and a program verification operation to an i-th one of the “n” program statuses in ascending order of level of the program statuses; and changing one or more of the memory cells of the first group of the memory cells having the i-th program status from the program permit mode to the program inhibit mode, and one or more of the memory cells of the second group of the memory cells having an (i+k)th program status to from the program inhibit mode to the program permit mode, upon success of the program verification operation to the i-th program status.

Claims

1. An operating method of a semiconductor memory device including a plurality of memory cells each having one of “

n”

number of program statuses as a target program status, the operating method comprising;

setting a first group of the memory cells, which have a first group of the program statuses as the target program status, to a program permit mode;

setting a second group of the memory cells, which have a second group of the program statuses as the target program status, to a program inhibit mode;

performing a program operation and a program verification operation to an i-th one of the “

n”

program statuses in ascending order of level of the program statuses; and

changing one or more of the memory cells of the first group of the memory cells having the i-th program status from the program permit mode to the program inhibit mode, and one or more of the memory cells of the second group of the memory cells having an (i+k)th program status to from the program inhibit mode to the program permit mode, upon success of the program verification operation to the i-th program status.

2. The operating method of claim 1, wherein the performing of the program operation includes:

providing a program permit voltage to the first group of the memory cells; and

providing a program inhibit voltage to the second group of the memory cells.

3. The operating method of claim 1, wherein the changing comprises:

determining the success of the program verification operation to the i-th program status when threshold voltages of the memory cells having the i-th program status reaches the i-th program status.

4. An operating method of the semiconductor memory device including a plurality of memory cells each having one of “

n”

number of program statuses as a target program status, the operating method comprising;

performing a program operation to the memory cells according to one of first to third program mode set until a first condition is met;

performing the program operation to the memory cells according to another one of first to third program mode set until a second condition is met; and

performing the program operation to the memory cells according to a remaining one of first to third program mode set.

5. The operating method of claim 4, wherein the performing of the program operation includes:

providing a program permit voltage to the memory cells of a program permit mode; and

providing a program inhibit voltage to the memory cells of a program inhibit mode.

6. The operating method of claim 4,

wherein the first condition is success of the program verification operation to a p-th program status, and

wherein the second condition is success of the program verification operation to a q-th program status.

7. The operating method of claim 4,

wherein the first condition is that a number of applied program pulses reaches a first reference number, and

wherein the second condition is that a number of applied program pulses reaches a second reference number.

8. The operating method of claim 4, wherein the first program mode set defines the memory cells having a target program statuses of first to third program statuses as a program permit mode, and defines the memory cells having the target program statuses of fourth to seventh program statuses as a program inhibit mode.

9. The operating method of claim 4, wherein the second program mode set defines the memory cells having a target program statuses of first, second, sixth and seventh program statuses as the program inhibit mode, and the memory cells having the target program statuses of third to fifth program statuses as the program permit mode.

10. The operating method of claim 4, wherein the third program mode set defines the memory cells having a target program statuses of first to fourth program statuses as the program inhibit mode, and the memory cells having the target program statuses of fifth to seventh program statuses as the program permit mode.

11. A semiconductor memory device, comprising:

a plurality of memory cells each having one of “

n”

number of program statuses as a target program status; and

a peripheral circuit suitable for;

setting a first group of the memory cells, which have a first group of the program statuses as the target program status, to a program permit mode;

setting a second group of the memory cells, which have a second group of the program statuses as the target program status, to a program inhibit mode;

performing a program operation and a program verification operation to an i-th one of the “

n”

program statuses in ascending order of level of the program statuses; and

changing one or more of the memory cells of the first group of the memory cells having the i-th program status from the program permit mode to the program inhibit mode, and one or more of the memory cells of the second group of the memory cells having an (i+k)th program status to from the program inhibit mode to the program permit mode, upon success of the program verification operation to the i-th program status.

12. The semiconductor memory device of claim 11, wherein the peripheral circuit provides a program permit voltage to the first group of the memory cells, and provides a program inhibit voltage to the second group of the memory cells during the program operation.

13. The semiconductor memory device of claim 11, wherein the peripheral circuit determines the success of the program verification operation to the i-th program status when threshold voltages of the memory cells having the i-th program status reaches the i-th program status during the changing.

14. A semiconductor memory device, comprising:

a plurality of memory cells each having one of “

n”

number of program statuses as a target program status; and

a peripheral circuit suitable for;

performing a program operation to the memory cells according to one of first to third program mode set until a first condition is met;

performing the program operation to the memory cells according to another one of first to third program mode set until a second condition is met; and

performing the program operation to the memory cells according to a remaining one of first to third program mode set.

15. The semiconductor memory device of claim 14, wherein the peripheral circuit provides a program permit voltage to the memory cells of a program permit mode, and provides a program inhibit voltage to the memory cells of a program inhibit mode.

16. The semiconductor memory device of claim 14,

wherein the first condition is success of the program verification operation to a p-th program status, and

wherein the second condition is success of the program verification operation to a q-th program status.

17. The semiconductor memory device of claim 14,

wherein the first condition is that a number of applied program pulses reaches a first reference number, and

wherein the second condition is that a number of applied program pulses reaches a second reference number.

18. The semiconductor memory device of claim 14, wherein the first program mode set defines the memory cells having a target program statuses of first to third program statuses as a program permit mode, and defines the memory cells having the target program statuses of fourth to seventh program statuses as a program inhibit mode.

19. The semiconductor memory device of claim 14, wherein the second program mode set defines the memory cells having a target program statuses of first, second, sixth and seventh program statuses as the program inhibit mode, and the memory cells having the target program statuses of third to fifth program statuses as the program permit mode.

20. The semiconductor memory device of claim 14, wherein the third program mode set defines the memory cells having a target program statuses of first to fourth program statuses as the program inhibit mode, and the memory cells having the target program statuses of fifth to seventh program statuses as the program permit mode.