THREE-DIMENSIONAL NAND DEVICE CONTAINING SUPPORT PEDESTAL STRUCTURES FOR A BURIED SOURCE LINE AND METHOD OF MAKING THE SAME

• US 20170148810A1
• Filed: 08/01/2016
• Published: 05/25/2017
• Est. Priority Date: 11/20/2015
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Inventors: Liu, Jin, Kai, James, Alsmeier, Johann, Zhang, Yanli
• Granted Patent: US 9,831,266 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/76895 Local interconnects; Local pads, as exemplified by patent document EP0896365
• CPC Class Codes: H01L 23/535 including internal interconnections, e.g. cross-under constructions internal lead connections H01L23/481
• CPC Class Codes: H01L 29/40117 the electrodes comprising a charge-trapping insulator
• CPC Class Codes: H01L 29/42344 with at least one additional gate, e.g. program gate, erase gate or select gate
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND

Abstract

A three-dimensional memory device includes an alternating stack of electrically conductive layers and insulating layers located over a substrate, an array of memory stack structures. An alternating sequence of support pedestal structures and conductive rail structures extending along a same horizontal direction are provided between the substrate and the alternating stack. Each memory stack structure straddles a vertical interface between a conductive rail structure and a support pedestal structure. A semiconductor channel in each memory stack structure contacts a respective conductive rail structure, and is electrically isolated from an adjacent support pedestal structure by a portion of a memory film. The conductive rail structures can function as source regions of memory device.

Claims

1. A three-dimensional memory device comprising:

an alternating stack of electrically conductive layers and insulating layers located over a substrate;

an array of memory stack structures, each memory stack structure extending through the alternating stack and including a memory film and a semiconductor channel laterally surrounded by the memory film; and

support structures located between the alternating stack and the substrate.

2. The three-dimensional memory device of claim 1, further comprising:

a source conductive layer underlying the alternating stack and overlying the substrate and contacting the support structures; and

conductive rail structures laterally extending along a first horizontal direction, contacting a top surface of the source conductive layer, and contacting sidewalls of the semiconductor channels.

3. The three-dimensional memory device of claim 2, wherein each of the conductive rail structures comprises dimpled sidewalls including respective planar vertical sidewalls adjoined by respective concave vertical sidewalls.

4. The three-dimensional memory device of claim 2, wherein:

each semiconductor channel contacts a sidewall of a respective conductive rail structure.

5. The three-dimensional memory device of claim 4, wherein each memory film contacts a sidewall of a respective support structure.

6. The three-dimensional memory device of claim 2, wherein top surfaces of the support structures are within a same horizontal plane as top surfaces of the conductive rail structures.

7. The three-dimensional memory device of claim 2, wherein:

the support structures comprise a support pedestal structures comprising a first semiconductor material having a doping of a first conductivity type and insulating barrier material below the first semiconductor material; and

the conductive rail structures comprise a second semiconductor material having a doping of a second conductivity type that is the opposite of the first conductivity type.

8. The three-dimensional memory device of claim 2, further comprising a backside contact via structure contacting a top surface of the source conductive layer.

9. The three-dimensional memory device of claim 8, further comprising an insulating spacer laterally surrounding the backside contact via structure and contacting the top surface of the source conductive layer,

10. The three-dimensional memory device of claim 9, wherein the conductive rail structures are laterally spaced from the backside contact via structure by the insulating spacer.

11. The three-dimensional memory device of claim 1, wherein each of the support structures comprises dimpled sidewalls including respective planar vertical sidewalls adjoined by respective concave vertical sidewalls.

12. The three-dimensional memory device of claim 11, wherein each of the concave vertical sidewalls of the support structures contacts an outer sidewall of a respective memory film.

13. The three-dimensional memory device of claim 1, wherein:

the three-dimensional memory device comprises a vertical NAND device located over the substrate;

the electrically conductive layers comprise, or are electrically connected to, a respective word line of the NAND device;

the substrate comprises a silicon substrate;

the vertical NAND device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;

at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;

the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon; and

the array of monolithic three-dimensional NAND strings comprises;

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;

a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and

a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level.

14. A method of forming a three-dimensional memory device, comprising:

forming a layer containing support pedestal structures and sacrificial material portions over a substrate;

forming an alternating stack of insulator layers and spacer material layers over the support pedestal structures and the sacrificial material portions;

forming memory stack structures through the alternating stack, wherein each of the memory stack structures comprises a respective portion of a memory film and a respective semiconductor channel, and protrudes into a respective sacrificial material portion;

removing the sacrificial material portions without removing the support pedestal structures to form at least one laterally-extending cavity;

removing portions of the memory film physically exposed to the at least one laterally extending cavity, while not removing portions of the memory film contacting the support pedestal structures; and

forming conductive rail structures in the at least one laterally-extending cavity and on sidewalls of the semiconductor channels.

15. The method of claim 14, further comprising forming a source conductive layer over the substrate, wherein the layer containing the support pedestal structures and the sacrificial material portions is formed on the source conductive layer.

16. The method of claim 14, further comprising forming memory openings through the alternating stack and into the layer containing the support pedestal structures and the sacrificial material portions, wherein each of the memory openings extends through a portion of a respective support pedestal structure and a respective sacrificial material portion.

17. The method of claim 16, wherein:

each memory film contacts a sidewall and a recessed horizontal surface of a respective support pedestal structure and a sidewall and a recessed horizontal surface of a respective sacrificial material portion;

concave sidewalls are formed on the support pedestal structures during formation of the memory openings by removal of portions of the support pedestal structures; and

each of the support pedestal structures comprises dimpled sidewalls including respective planar vertical sidewalls adjoined by respective concave vertical sidewalls.

18. The method of claim 14, wherein each of the conductive rail structures comprises dimpled sidewalls including respective planar vertical sidewalls adjoined by respective concave vertical sidewalls.

19. The method of claim 14, wherein:

the support pedestal structures comprises a first semiconductor material having a doping of a first conductivity type;

the sacrificial material portions comprises an undoped semiconductor material; and

the sacrificial material portions are removed without removing the support pedestal structures employing a wet etch process that removes the undoped semiconductor material selective to the first semiconductor material.

20. The method of claim 19, wherein:

the first semiconductor material comprises p-doped amorphous silicon;

the undoped semiconductor material comprises undoped amorphous silicon; and

the wet etch process employs a solution including trimethyl-2 hydroxyethyl ammonium hydroxide as an etchant.

21. The method of claim 14, further comprising:

forming a backside contact trench extending through the alternating stack and through the sacrificial material portions; and

introducing an etchant that etches a material of the sacrificial material portions selective to materials of the support pedestal structures through the backside contact trench, wherein the at least one laterally-extending cavity is formed by removal of the sacrificial material portions.

22. The method of claim 21, further comprising:

forming an insulating spacer on sidewalls of the conductive rail structures and on a sidewall of the backside contact trench;

forming a backside contact via structure in the insulating spacer; and

forming a source conductive layer over the substrate.

23. The method of claim 22, wherein the layer containing the support pedestal structures and the sacrificial material portions is formed on the source conductive layer, and wherein the backside contact via structure is formed directly on a top surface of the source conductive layer.

24. The method of claim 14, wherein:

the three-dimensional memory device comprises a vertical NAND device located over the substrate;

the spacer material layers are formed as, or are replaced with, electrically conductive layers;

the electrically conductive layers comprise, or are electrically connected to, a respective word line of the NAND device;

the substrate comprises a silicon substrate;

the vertical NAND device comprises an array of monolithic three-dimensional NAND strings over the silicon substrate;

at least one memory cell in a first device level of the array of monolithic three-dimensional NAND strings is located over another memory cell in a second device level of the array of monolithic three-dimensional NAND strings;

the silicon substrate contains an integrated circuit comprising a driver circuit for the memory device located thereon; and

the array of monolithic three-dimensional NAND strings comprises;

a plurality of semiconductor channels, wherein at least one end portion of each of the plurality of semiconductor channels extends substantially perpendicular to a top surface of the substrate;

a plurality of charge storage elements, each charge storage element located adjacent to a respective one of the plurality of semiconductor channels; and

a plurality of control gate electrodes having a strip shape extending substantially parallel to the top surface of the substrate, the plurality of control gate electrodes comprise at least a first control gate electrode located in a first device level and a second control gate electrode located in a second device level.