METAL OXIDE SEMICONDUCTOR FIELD EFFECT TRANSISTOR POWER DEVICE WITH MULTI GATES CONNECTION

• US 20170148889A1
• Filed: 03/01/2016
• Published: 05/25/2017
• Est. Priority Date: 11/23/2015
• Status: Abandoned Application

• Current Assignee: PFC Device Holdings Ltd. (PFC Device, Inc.)
• Original Assignee: PFC Device Holdings Ltd. (PFC Device, Inc.)
• Inventors: CHEN, Kuan-Yu, LI, Hsu-Heng, CHEN, Mei-Ling
• Application Number:
  US15/057,931
• Publication Number:
  US 20170148889A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 28/00 Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor testing or measuring during manufacture H01L22/00; integration methods H01L21/70; integrated circuits H01L27/00; two-terminal components with a potential-jump or surface barrier H01L29/00; resistors in general H01C; inductors in general H01F; capacitors in general H01G
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4925 with a multiple layer structure, e.g. several silicon layers with different crystal structure or grain arrangement with only a vertical doping structure or vertical doping variation H01L29/4916
• CPC Class Codes: H01L 29/66484 with multiple gate, at least one gate being an insulated gate H01L29/66742 takes precedence
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645

Abstract

A metal oxide semiconductor field effect transistor (MOSFET) power device with multi gates connection includes a first-conductive type substrate, a first-conductive type epitaxial layer arranged on the first-conductive type substrate, a plurality of device trenches defined on an upper face of the first-conductive type epitaxial layer. Each of the device trenches has, from bottom of the trench to top of the trench, a bottom gate, a split gate and a trench gate. A bottom insulating layer is formed between the bottom gate and the bottom of the trench, an intermediate insulating layer is formed between the bottom gate and the split gate, an upper insulating layer is formed between the split gate and the trench gate.

Claims

1. A metal oxide semiconductor field effect transistor (MOSFET) power device with multi gates connection, comprising:

a first-conductive type substrate;

a first-conductive type epitaxial layer arranged on the first-conductive type substrate; and

a plurality of device trenches defined on an upper face of the first-conductive type epitaxial layer, each of the device trenches having, from bottom of the trench to top of the trench, a bottom gate, a split gate and a trench gate,

wherein a bottom insulating layer is formed between the bottom gate and the first-conductive type epitaxial layer, an intermediate insulating layer is formed between the bottom gate and the split gate, and an upper insulating layer is formed between the split gate and the trench gate.

2. The MOSFET power device in claim 1, wherein the bottom gate, the split gate and the trench gate are made of polysilicon.

3. The MOSFET power device in claim 1, wherein the bottom gate is electrically isolated with the split gate and the trench gate.

4. The MOSFET power device in claim 1, wherein the bottom gate is thermal oxide or deposited oxide.

5. The MOSFET power device in claim 1, wherein the intermediate insulating layer and the upper insulating layer are deposited oxide.

6. The MOSFET power device in claim 1, further comprising a second conductive type body area outside the device trench and a first conductive type source region at upper portion of the second conductive type body area.

7. The MOSFET power device in claim 1, wherein the first conductive type is N type or P type.

8. The MOSFET power device in claim 6, further comprising:

an interlayer dielectric (ILD) layer arranged atop the trench gate and the first conductive type source region; and

a contact metal layer arranged atop the ILD layer.

9. A method for manufacturing metal oxide semiconductor field effect transistor (MOSFET) power device with multi gates connection, comprising:

providing a first-conductive type substrate and a first-conductive type epitaxial layer arranged on the first-conductive type substrate;

defining a plurality of device trenches defined on an upper face of the first-conductive type epitaxial layer, each of the device trenches having, from bottom of the trench to top of the trench, a bottom gate, a split gate and a trench gate,

wherein a bottom insulating layer is formed between the bottom gate and the first-conductive type epitaxial layer, an intermediate insulating layer is formed between the bottom gate and the split gate, and an upper insulating layer is formed between the split gate and the trench gate.

10. The method in claim 9, wherein the bottom gate, the split gate and the trench gate are made of polysilicon.

11. The method in claim 9, wherein the bottom gate is electrically isolated with the split gate and the trench gate.

12. The method in claim 9, wherein the bottom gate is thermal oxide or deposited oxide.

13. The method in claim 9, wherein the intermediate insulating layer and the upper insulating layer are deposited oxide.

14. The method in claim 9, further comprising:

forming a second conductive type body area outside the device trench, and forming a first conductive type source region at upper portion of the second conductive type body area

15. The method in claim 9, wherein the first conductive type is N type or P type.

16. The method in claim 9, further comprising:

forming an interlayer dielectric (ILD) layer arranged atop the trench gate and the first conductive type source region; and

forming a contact metal layer arranged atop the ILD layer.