Network Processors

• US 20170150242A1
• Filed: 11/23/2016
• Published: 05/25/2017
• Est. Priority Date: 11/25/2015
• Status: Active Grant

• Current Assignee: Avago Technologies International Sales Pte Limited (Broadcom, Inc.)
• Original Assignee: Broadcom Corporation (Broadcom, Inc.)
• Inventors: KOREN, Asaf, Weitz, Eliezer, Harel, Koby, Ben Yaacov, Hilla, Baum-Mizrachi, Tal, Naaman, Ifat, Pomeranz, Yanai, Aviram, Yariv, Joffe, Ira, Wolach, Oren Issac, Amitai, Assaf, Pasternak, Daniel, Gorsetman, Yoram, McGee, Mitchell Gordon, Sitton, Gal, Hirth, Ryan
• Granted Patent: US 10,541,935 B2
• Time in Patent Office: Days
• CPC Class Codes: H04L 47/125 by balancing the load, e.g. traffic engineering
• CPC Class Codes: H04L 47/6255 queue load conditions, e.g. longest queue first
• CPC Class Codes: H04L 49/9015 for supporting a linked list
• CPC Class Codes: H04L 49/9057 Arrangements for supporting packet reassembly or resequencing
• CPC Class Codes: H04L 49/9078 using an external memory or storage device
• CPC Class Codes: H04Q 11/0066 Provisions for optical burst or packet networks
• CPC Class Codes: H04Q 2011/0077 Labelling aspects, e.g. multiprotocol label switching [MPLS], G-MPLS, MPAS

Abstract

The present disclosure is directed to a network processor for processing high volumes of traffic provided by todays access networks at (or near) wireline speeds. The network process can be implemented within a residential gateway to perform, among other functions, routing to deliver high speed data services (e.g., data services with rates up to 10 Gbit/s) from a wide area network (WAN) to end user devices in a local area network (LAN).

Claims

1. A network processor comprising:

a packet processor grid comprising a plurality of packet processors;

a dispatcher configured to provide a plurality of packet descriptors from a linked list to the plurality of packet processors to process the plurality of packet descriptors; and

accelerator circuits configured to perform hardware based acceleration of packet processing tasks on behalf of the plurality of packet processors to process the plurality of packet descriptors, wherein the accelerator circuits are implemented in a different clock domain than the plurality of packet processors and are accessed by the plurality of packet processors via a communication bus.

2. The network processor of claim 1, wherein the dispatcher is further configured to provide each of the plurality of packet descriptors to one of the plurality of packet processors based on utilizations of the plurality of packet processors.

3. The network processor of claim 1, wherein the dispatcher is further configured to store the plurality of packet descriptors in the linked list based on an order in which the plurality of packet descriptors are received by the dispatcher.

4. The network processor of claim 3, further comprising:

a reorderer configured to receive the plurality of packet descriptors from the plurality of packet processors after the plurality of packet descriptors have been processed.

5. The network processor of claim 4 wherein the reorderer is further configured to store each of the plurality of packet descriptors in a same position in the linked list in which the packet descriptor was stored by the dispatcher.

6. The network processor of claim 5, wherein the reorderer is further configured to provide processed packet descriptors from the linked list as output until a head of the linked list is empty.

7. The network processor of claim 1, further comprising:

a queue manager configured to queue one of the plurality of packet descriptors, processed by one of the plurality of packet processors, in an egress queue for transmission.

8. The network processor of claim 7, wherein the queue manager is further configured to move a packet payload associated with the one of the plurality of packet descriptors from an internal memory of the network processor to an external memory of the network processor based on an indication in the one of the plurality of packet descriptors.

9. The network processor of claim 7, wherein the queue manager is further configured to move a packet payload associated with the one of the plurality of packet descriptors from an internal memory of the network processor to an external memory of the network processor based on an indication in configuration information of the egress queue.

10. The network processor of claim 7, wherein the queue manager is further configured to move a packet payload associated with the one of the plurality of packet descriptors from an internal memory of the network processor to an external memory of the network processor based on an occupancy of the internal memory exceeding an internal memory threshold assigned to the egress queue.

11. The network processor of claim 7, wherein the queue manager is further configured to move a packet payload associated with the one of the plurality of packet descriptors from an internal memory of the network processor to an external memory of the network processor based on an occupancy of the egress queue exceeding an egress queue occupancy threshold.

12. A method comprising:

receiving a plurality of packet descriptors;

storing the plurality of packet descriptors in a linked list based on an order in which the plurality of packet descriptors are received;

providing each of the plurality of packet descriptors from the linked list to one of a plurality of packet processors based on utilizations of the plurality of packet processors;

storing each of the plurality of packet descriptors in a same position in the linked list in which the packet descriptor was stored before being processed by the one of the plurality of packet processors; and

providing processed packet descriptors from the linked list as output until a head of the linked list is empty.

13. The method of claim 12, further comprising:

queuing one of the processed packet descriptors provided from the linked list in an egress queue for transmission.

14. The method of claim 13, further comprising:

moving a packet payload associated with the one of the processed packet descriptors from an internal memory of a network processor to an external memory of the network processor based on an indication in the processed packet descriptor.

15. The method of claim 13, further comprising:

moving a packet payload associated with the one of the processed packet descriptors from an internal memory of a network processor to an external memory of the network processor based on an indication in configuration information of the egress queue.

16. The method of claim 13, further comprising;

moving a packet payload associated with the one of the processed packet descriptors from an internal memory of a network processor to an external memory of the network processor based on an occupancy of the internal memory exceeding an internal memory threshold assigned to the egress queue.

17. The method of claim 13, further comprising:

moving a packet payload associated with the one of the processed packet descriptors from an internal memory of a network processor to an external memory of the network processor based on an occupancy of the egress queue exceeding an egress queue occupancy threshold.

18. A network processor comprising:

a packet processor grid comprising a plurality of packet processors;

a dispatcher configured to receive a plurality of packet descriptors, store the plurality of packet descriptors in a linked list based on an order in which the plurality of packet descriptors are received by the dispatcher, and provide each of the plurality'"'"' of packet descriptors from the linked list to one of the plurality of packet processors based on utilizations of the plurality of packet processors; and

a reorderer configured to receive the plurality of packet descriptors from the plurality of packet processors, store each of the plurality of packet descriptors in a same position in the linked list in which the packet descriptor was stored by the dispatcher, and provide packet descriptors from the linked list as output until a head of the linked list is empty.

19. The network processor of claim 18, further comprising:

a queue manager configured to queue one of the plurality of packet descriptors, processed by one of the plurality of packet processors, in an egress queue for transmission.

20. The network processor of claim 19, wherein the queue manager is further configured to move a packet payload associated with the one of the plurality of packet descriptors from an internal memory of the network processor to an external memory of the network processor based on an occupancy of the internal memory and an occupancy of the egress queue.