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Network Processors

  • US 20170150242A1
  • Filed: 11/23/2016
  • Published: 05/25/2017
  • Est. Priority Date: 11/25/2015
  • Status: Active Grant
First Claim
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1. A network processor comprising:

  • a packet processor grid comprising a plurality of packet processors;

    a dispatcher configured to provide a plurality of packet descriptors from a linked list to the plurality of packet processors to process the plurality of packet descriptors; and

    accelerator circuits configured to perform hardware based acceleration of packet processing tasks on behalf of the plurality of packet processors to process the plurality of packet descriptors, wherein the accelerator circuits are implemented in a different clock domain than the plurality of packet processors and are accessed by the plurality of packet processors via a communication bus.

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