SEMICONDUCTOR DEVICE, DATA PROCESSING SYSTEM, AND SEMICONDUCTOR DEVICE CONTROL METHOD

• US 20170153838A1
• Filed: 11/18/2016
• Published: 06/01/2017
• Est. Priority Date: 11/30/2015
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: MATSUBARA, Katsushige, HASHIMOTO, Ryoji, NAKAZAWA, Kimihiko, IRITA, Takahiro, TSUDA, Tetsuji, MOCHIZUKI, Seiji, KAYA, Toshiyuki
• Granted Patent: US 10,459,646 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 2207/544 Indexing scheme relating to group G06F7/544
• CPC Class Codes: G06F 3/0604 Improving or facilitating administration, e.g. storage management
• CPC Class Codes: G06F 3/0638 Organizing or formatting or addressing of data
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G06F 7/544 for evaluating functions by calculation G06F7/4824 takes precedence
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence

Abstract

Disclosed is a semiconductor device capable of performing compression and decompression with increased appropriateness. The semiconductor device includes a computing module and a memory control module. The computing module includes a computing unit and a compression circuit. The computing unit performs arithmetic processing. The compression circuit compresses data indicative of the result of arithmetic processing. The memory control module includes an access circuit and a decompression circuit. The access circuit writes compressed data into a memory and reads written data from the memory. The decompression circuit decompresses data read from the memory and outputs the decompressed data to the computing module.

Claims

1. A semiconductor device comprising:

a computing module; and

a memory control module,

wherein the computing module includes;

an arithmetic processing section that performs arithmetic processing; and

a compression section that compresses data indicative of the result of the arithmetic processing, and

wherein the memory control module includes;

an access section that writes the compressed data into a memory and reads the written data from the memory; and

a decompression section that decompresses data read from the memory and outputs the decompressed data to the computing module.

2. The semiconductor device according to claim 1, further comprising:

a conversion section that converts data indicative of the result of the arithmetic processing to data formed in units of compression processing,

wherein the compression section compresses the data in units of the compression processing.

3. The semiconductor device according to claim 2,

wherein the conversion section converts the data indicative of the result of the arithmetic processing to data structured to have a predetermined length and consecutive addresses.

4. The semiconductor device according to claim 2,

wherein the conversion section is a buffer that stores the data indicative of the result of the arithmetic processing in units of the compression processing.

5. The semiconductor device according to claim 4,

wherein the arithmetic processing section sequentially outputs data having non-consecutive addresses in units of the arithmetic processing, and

wherein the buffer stores the outputted data in such a manner that the outputted data have consecutive addresses.

6. The semiconductor device according to claim 1,

wherein, when data read from the memory is compressed, the decompression section decompresses the data.

7. The semiconductor device according to claim 6,

wherein, when reading data from the memory, the arithmetic processing section outputs a memory read command and a flag indicative of whether the data is compressed or uncompressed, and

wherein, when data read from the memory is compressed, the decompression section decompresses the data in accordance with the flag.

8. The semiconductor device according to claim 1,

wherein the compression section compresses data in predetermined compression units and writes the compressed data into the memory with initial addresses of the compression units being identical with corresponding addresses used before compression.

9. The semiconductor device according to claim 1,

wherein the memory control module includes an address conversion section that converts an address requested by the computing module, and

wherein the access section accesses the memory in accordance with the converted address.

10. The semiconductor device according to claim 9,

wherein the decompression section decompresses the data when the requested address is included in a first address area and does not decompress the data when the requested address is included in a second address area.

11. The semiconductor device according to claim 10,

wherein an address area obtained by converting the first address area and an address area obtained by converting the second address area are included in the same address area of the memory.

12. The semiconductor device according to claim 9,

wherein the compression section compresses data in predetermined compression units and requests the data in the compression units to be written into the memory, and

wherein the address conversion section converts the address in such a manner that a plurality of data in the compression units are included in the same address area of the memory.

13. The semiconductor device according to claim 12,

wherein the decompression section decompresses data in a first memory area within address areas of the memory when the requested address is included in a first address area, and decompresses data in a second memory area within the address areas of the memory when the requested address is included in a second address area.

14. A data processing system comprising:

a semiconductor device; and

a memory that stores data of the semiconductor device,

wherein the semiconductor device includes a computing module and a memory control module,

wherein the computing module includes;

an arithmetic processing section that performs arithmetic processing; and

a compression section that compresses data indicative of the result of the arithmetic processing, and

wherein the memory control module includes;

an access section that writes the compressed data into the memory and reads the written data from the memory; and

a decompression section that decompresses data read from the memory and outputs the decompressed data to the computing module.

15. A semiconductor device control method for a semiconductor device having a computing module and a memory control module, the semiconductor device control method comprising the steps of:

performing, with the computing module, arithmetic processing;

compressing, with the computing module, data indicative of the result of the arithmetic processing;

writing, with the memory control module, the compressed data into a memory and reading the written data from the memory; and

decompressing, with the memory control module, data read from the memory and outputting the decompressed data to the computing module.