SYSTEM ARCHITECTURE WITH MEMORY CHANNEL DRAM FPGA MODULE

• US 20170153854A1
• Filed: 03/30/2016
• Published: 06/01/2017
• Est. Priority Date: 11/30/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Hongzhong Zheng, Mu-Tien Chang
• Inventors: ZHENG, Hongzhong, CHANG, Mu-Tien
• Granted Patent: US 10,013,212 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0802 Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
• CPC Class Codes: G06F 12/1009 using page tables, e.g. page table structures
• CPC Class Codes: G06F 2009/45583 Memory management, e.g. access or allocation
• CPC Class Codes: G06F 2212/1024 Latency reduction
• CPC Class Codes: G06F 2212/152 Virtualized environment, e.g. logically partitioned system
• CPC Class Codes: G06F 2212/621 Coherency control relating to peripheral accessing, e.g. from DMA or I/O device
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0665 at area level, e.g. provisioning of virtual or logical volumes
• CPC Class Codes: G06F 3/0689 Disk arrays, e.g. RAID, JBOD
• CPC Class Codes: G06F 9/45558 Hypervisor-specific management and integration aspects

Abstract

An accelerator controller comprises a detector and a loader. The detector detects runtime features of an application or a virtual machine and identifies an accelerator logic associated with the application or the virtual machine corresponding to the detected runtime features. The loader loads the identified accelerator logic into at least one dynamic random access memory (DRAM). The at least one DRAM array is selectively reconfigurable to behave like a look-up table (LUT) or to behave like a DRAM memory array based on the identified accelerator logic, and the at least one DRAM array is in a cache-coherent address space of the operating system environment. The accelerator logic may comprise a look-up table (LUT).

Claims

1. An accelerator controller, comprising:

a detector to detect runtime features of an application or a virtual machine and to identify an accelerator logic associated with the application or the virtual machine corresponding to the detected runtime features; and

a loader to load the identified accelerator logic into at least one dynamic random access memory (DRAM), the at least one DRAM array being selectively reconfigurable to behave like a look-up table (LUT)based on the identified accelerator logic.

2. The accelerator controller according to claim 1, further comprising the at least one DRAM.

3. The accelerator controller according to claim 1, wherein the at least one DRAM array is in a cache-coherent address space of the operating system environment.

4. The accelerator controller according to claim 1, wherein the runtime features are based on a predefined identification of the application or the virtual machine.

5. The accelerator controller according to claim 1, wherein the runtime features are based on at least one of a function utilization, a central processing utilization, a memory utilization, and a latency associated with the application or the virtual machine.

6. The accelerator controller according to claim 1, wherein the accelerator logic comprises a look-up table (LUT).

7. The accelerator controller according to claim 1, wherein the at least one DRAM array is part of a Dual In-line Memory Module (DIMM).

8. The accelerator controller according to claim 7, wherein the DIMM further comprises at least one DRAM array that is not selectively reconfigurable to behave like a look-up table (LUT) or to behave like a DRAM memory array.

9. The accelerator controller according to claim 1, wherein the identified accelerator logic is loaded in the at least one DRAM array using load and store commands.

10. An accelerator controller, comprising:

a detector to detect runtime features of an application or a virtual machine, the runtime features being based on at least one of a predefined identification of the application or the virtual machine, a function utilization, a central processing utilization, a memory utilization, and a latency associated with the application or the virtual machine; and

a loader to load an accelerator logic corresponding to the detected runtime features into at least one dynamic random access memory (DRAM), the at least one DRAM array being selectively reconfigurable to behave like a look-up table (LUT) based on the identified accelerator logic.

11. The accelerator controller according to claim 10, wherein the detector further identifies an accelerator logic associated with the application or the virtual machine corresponding to the detected runtime features.

12. The accelerator controller according to claim 10, wherein the at least one DRAM array is in a cache-coherent address space of the system.

13. The accelerator logic according to claim 10, wherein the accelerator logic comprises a look-up table (LUT).

14. The accelerator logic according to claim 10, wherein the DRAM array is part of a Dual In-line Memory Module (DIMM).

15. The accelerator logic according to claim 14, wherein the DIMM further comprises at least one DRAM array that is not selectively reconfigurable to behave like a look-up table (LUT) or to behave like a DRAM memory array.

17. The method according to claim 15, wherein the at least one DRAM sub-array is selectively reconfigurable to behave like a look-up table (LUT),

wherein the at least one DRAM sub-array is configured to behave like an LUT,

wherein the at least one DRAM sub-array is in a cache-coherent address space of the operating system environment,

wherein the at least one DRAM sub-array is part of a Dual In-line Memory Module (DIMM), and

wherein the detected the runtime features are based on at least one of a predefined identification of the application or the virtual machine, a function utilization, a central processing utilization, a memory utilization, a latency associated with the application or the virtual machine.

16. A method, comprising:

detecting runtime features of an application or a virtual machine running in an operating system environment;

identifying an accelerator logic corresponding to the detected runtime features; and

loading the selected accelerator logic into at least one dynamic random access memory (DRAM) sub-array using load and store commands.

18. The method of claim 16, wherein the accelerator logic comprises a look-up table (LUT).

19. The method of claim 16, wherein the selected accelerator logic is loaded in the at least one DRAM sub-array by an acceleration controller.

20. The method of claim 16, wherein the selected accelerator logic is loaded into the at least one DRAM by the application or by the virtual machine.