FAN-OUT SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME

• US 20170154838A1
• Filed: 10/26/2016
• Published: 06/01/2017
• Est. Priority Date: 11/26/2015
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electro-Mechanics Co., Ltd. (Samsung Group)
• Inventors: KIM, Yoon Su, BAEK, Seung Min, KO, Young Gwan
• Application Number:
  US15/335,120
• Publication Number:
  US 20170154838A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/4857 Multilayer substrates multilayer metallisation on monolayer substrate H01L21/4846
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 2224/04105 Bonding areas formed on an encapsulation of the semiconductor or solid-state body, e.g. bonding areas on chip-scale packages
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/131 with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/16227 the bump connector connecting to a bond pad of the item
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/73204 the bump connector being embedded into the layer connector
• CPC Class Codes: H01L 2225/1035 the device being entirely enclosed by the support, e.g. high-density interconnect [HDI]
• CPC Class Codes: H01L 2225/1041 Special adaptations for top connections of the lowermost container, e.g. redistribution layer, integral interposer
• CPC Class Codes: H01L 2225/1058 Bump or bump-like electrical connections, e.g. balls, pillars, posts
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/4827 Materials
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/16 of an individual bump connector
• CPC Class Codes: H01L 24/19 Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/20 : Structure, shape, material or disposition of high density interconnect preforms
• CPC Class Codes: H01L 24/32 : of an individual layer connector
• CPC Class Codes: H01L 24/73 : Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/105 : the devices being of a type provided for in group H01L27/00
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/18162 : of a chip with build-up interconnect
• CPC Class Codes: H01L 2924/3025 : Electromagnetic shielding
• CPC Class Codes: H01L 2924/37001 : Yield

Abstract

A fan-out semiconductor package includes a semiconductor chip including a body and an electrode pad disposed on the body, a metal layer disposed on the electrode pad of the semiconductor chip, and a interconnection member including an insulating layer disposed on one side of the semiconductor chip, a via hole penetrating through the insulating layer and exposing at least a portion of a surface of the metal layer, a seed layer disposed on the surface of the metal layer exposed by the via hole and a wall of the via hole, and a conductor layer disposed on the seed layer.

Claims

1. A fan-out semiconductor package comprising:

a semiconductor chip including a body and an electrode pad disposed on the body;

a metal layer disposed on the electrode pad of the semiconductor chip; and

an interconnection member including an insulating layer disposed on one side of the semiconductor chip, a via hole penetrating through the insulating layer and exposing at least a portion of a surface of the metal layer, a seed layer disposed on the surface of the metal layer exposed by the via hole and a wall of the via hole, and a conductor layer disposed on the seed layer.

2. The fan-out semiconductor package of claim 1, wherein the metal layer includes:

an interlayer seed layer disposed on the electrode pad; and

an interlayer conductor layer disposed on the interlayer seed layer.

3. The fan-out semiconductor package of claim 2, wherein the conductor layer and the seed layer of the interconnection member are conterminous with each other, and the interlayer conductor layer and the interlayer seed layer of the metal layer are conterminous with each other.

4. The fan-out semiconductor package of claim 3, wherein an area of the interlayer conductor layer exposed by the via hole of the interconnection member is not equal to an area of the interlayer conductor layer.

5. The fan-out semiconductor package of claim 2, wherein the interlayer seed layer of the metal layer contains the same material as that of the seed layer of the interconnection member, and

the interlayer conductor layer of the metal layer contains the same material as that of the conductor layer of the interconnection member.

6. The fan-out semiconductor package of claim 5, wherein the interlayer seed layer contains one or more of titanium (Ti), titanium-tungsten (Ti—

W), molybdenum (Mo), chrome (Cr), nickel (Ni), and nickel-chrome (Ni—

Cr).

7. The fan-out semiconductor package of claim 5, wherein the interlayer conductor layer of the metal layer includes a first interlayer conductor layer disposed on the seed layer and containing copper (Cu).

8. The fan-out semiconductor package of claim 7, wherein the interlayer conductor layer of the metal layer further includes a second interlayer conductor layer disposed on the first interlayer conductor layer thereof and containing copper (Cu).

9. The fan-out semiconductor package of claim 5, wherein the seed layer of the interconnection member includes a first seed layer disposed on a surface of the interlayer conductor layer of the metal layer and the wall of the via hole and containing one or more of titanium (Ti), titanium-tungsten (Ti—

W), molybdenum (Mo), chrome (Cr), nickel (Ni), and nickel-chrome (Ni—

Cr); and

a second seed layer disposed on the first seed layer and containing copper (Cu).

10. The fan-out semiconductor package of claim 5, wherein the conductor layer contains copper (Cu).

11. The fan-out semiconductor package of claim 1, wherein the semiconductor chip further includes a passivation layer disposed on the body and covering a portion of the electrode pad.

12. The fan-out semiconductor package of claim 11, wherein the metal layer contacts the passivation layer, and

only a portion of the surface of the metal layer is exposed by the via hole.

13. The fan-out semiconductor package of claim 11, wherein the metal layer is partially disposed on the passivation layer, and

only a portion of the surface of the metal layer is exposed by the via hole.

14. The fan-out semiconductor package of claim 11, wherein the metal layer is spaced apart from the passivation layer, and

only a portion of the surface of the metal layer is exposed by the via hole.

15. The fan-out semiconductor package of claim 11, wherein the metal layer is spaced apart from the passivation layer, and

an entire surface of the metal layer is exposed by the via hole.

16. The fan-out semiconductor package of claim 1, wherein the body contains one or more of silicon (Si), germanium (Ge), and gallium arsenide (GaAs).

17. The fan-out semiconductor package of claim 1, wherein the electrode pad contains aluminum (Al).

18. A method of manufacturing a semiconductor chipa fan-out semiconductor package, comprising:

preparing a semiconductor chip including a body and an electrode pad disposed on the body;

forming a metal layer on the electrode pad; and

forming an interconnection member by forming an insulating layer on one side of the semiconductor chip, forming a via hole penetrating through the insulating layer and exposing at least a portion of a surface of the metal layer, forming a seed layer disposed on the surface of the metal layer exposed by the via hole and a wall of the via hole, and forming a conductor layer on the seed layer, the conductor layer filling the via hole.

19. The method of claim 18, wherein the forming of the metal layer on the electrode pad includes:

forming an interlayer seed layer on the electrode pad; and

electroplating an interlayer conductor layer on the interlayer seed layer, and

the conductor layer of the interconnection member is formed on the on the seed layer thereof by electroplating.

20. The method of claim 18, further comprising removing a natural oxide layer on a surface of the electrode pad by plasma, prior to forming the insulating layer of the interconnection member.