MEMORY SYSTEM THAT CARRIES OUT AN ATOMIC WRITE OPERATION

• US 20170160988A1
• Filed: 08/22/2016
• Published: 06/08/2017
• Est. Priority Date: 12/08/2015
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: NEMOTO, Hiroyuki, KOHARA, Shunitsu, KITSUNAI, Kazuya, ARAI, Satoshi
• Granted Patent: US 9,940,071 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]

Abstract

A memory system includes a non-volatile memory and a controller circuit. The controller circuit is configured to carry out an atomic write operation in the non-volatile memory in response to an atomic write command, and selectively carry out one of a first operation and a second operation corresponding to address mapping between a logical address and a physical address of the non-volatile memory, along with the atomic write operation. When the first operation is selected, the controller circuit starts to update the address mapping after receiving a notification that writing of all data of the atomic write operation has been completed. When the second operation is carried out, the controller circuit starts to update the address mapping before receiving the notification.

Claims

1. A memory system, comprising:

a non-volatile memory; and

a controller circuit configured to carry out an atomic write operation in the non-volatile memory in response to an atomic write command, and selectively carry out one of a first operation and a second operation corresponding to address mapping between a logical address and a physical address of the non-volatile memory, along with the atomic write operation, wherein

when the first operation is carried out, the controller circuit starts to update the address mapping after receiving a notification that writing of all data of the atomic write operation has been completed, and

when the second operation is carried out, the controller circuit starts to update the address mapping before receiving the notification.

2. The memory system according to claim 1, wherein

when the first operation is carried out, the controller circuit starts to update the address mapping by tracking a physical address in which data have been written, separately from the address mapping, and incorporating the tracked physical address in the address mapping, and

when the second operation is carried out, the controller circuit starts to update the address mapping without tracking the physical address separately from the address mapping.

3. The memory system according to claim 2, wherein

when a cancellation command is received while the atomic write operation is being carried out and the first operation is carried out, the controller circuit discards the tracked physical address, and

when the cancellation command is received while the atomic write operation is being carried out and the second operation is carried out, the controller circuit restores the address mapping to a state before the atomic write operation started.

4. The memory system according to claim 3, wherein

the controller circuit restores the address mapping by modifying a part of the address mapping that has been updated through the second operation.

5. The memory system according to claim 3, wherein

the address mapping is stored in a volatile memory and transferred periodically to the non-volatile memory, and

the controller circuit restores the address mapping in the volatile memory, by retrieving an address mapping that has been most recently transferred to the non-volatile memory and updating the retrieved address mapping for all data writing that have been performed except for the atomic write operation.

6. The memory system according to claim 2, wherein

when the atomic write command is for a first namespace, the controller circuit carries out the first operation, and

when the atomic write command is for a second namespace different from the first namespace, the controller circuit carries out the second operation.

7. The memory system according to claim 6, further comprising:

a volatile memory unit having a region for storing the physical address tracked by the controller circuit, wherein

when the atomic write command is for a third namespace different from the first and second namespaces, the controller circuit selectively carries out one of the first operation and the second operation based on a remaining capacity of the region.

8. The memory system according to claim 7, wherein

when the atomic write command is for the third namespace, the controller circuit selectively carries out one of the first operation and the second operation also based on whether an operation that has been carried out for another atomic write operation that is currently being carried out is the first operation or the second operation.

9. The memory system according to claim 8, wherein

when the atomic write command is for the third namespace, the controller circuit selectively carries out one of the first operation and the second operation also based on a probability that said another atomic write operation is cancelled before completion.

10. The memory system according to claim 8, wherein

when the controller circuit selects the first operation and the first operation has been carried out for said another atomic write operation, the controller circuit changes the operation for said another atomic write operation to the second operation.

11. The memory system according to claim 10, wherein

when the controller circuit changes the operation for said another atomic write operation to the second operation, the controller circuit starts to update the address mapping based on a tracked physical address for said another atomic write operation and then discards the tracked physical address.

12. A method for carrying out an atomic write operation with respect to a non-volatile memory, comprising:

starting an atomic write operation in the non-volatile memory, in response to an atomic write command;

selecting one of a first operation and a second operation corresponding to address mapping between a logical address and a physical address of the non-volatile memory;

when the first operation is selected, starting to update the address mapping after receiving a notification that writing of all data of the atomic write operation has been completed; and

when the second operation is selected, starting to update the address mapping before receiving the notification.

13. The method according to claim 12, wherein

when the first operation is selected, the updating of the address mapping is carried out by tracking a physical address in which data have been written, separately from the address mapping, and incorporating the tracked physical address to the address mapping, and

when the second operation is selected, the updating of the address mapping is carried out without tracking the physical address separately from the address mapping.

14. The method according to claim 13, further comprising:

receiving a cancellation command while the atomic write operation is being carried out;

when the first operation is selected for the atomic write operation, discarding the tracked physical address in response to the cancellation command; and

when the second operation is selected for the atomic write operation, restoring the address mapping to a state before the atomic write operation starts.

15. The method according to claim 14, wherein

the address mapping is restored by modifying a part of the address mapping that has been updated through the second operation.

16. The method according to claim 14, wherein

the address mapping is stored in a volatile memory and transferred periodically to the non-volatile memory, and

the address mapping in the volatile memory is restored, by retrieving an address mapping that has been most recently transferred to the non-volatile memory and updating the retrieved address mapping for all data writing that have been performed except for the atomic write operation.

17. The method according to claim 13, wherein

when the atomic write command is for a first namespace, the first operation is selected, and

when the atomic write command is for a second namespace different from the first namespace, the second operation is selected.

18. The method according to claim 17, wherein

when the atomic write command is for a third namespace different from the first and second namespaces, one of the first operation and the second operation is selected based on a remaining capacity of a region for storing the tracked physical address.

19. The method according to claim 18, wherein

when the atomic write command is for the third namespace, said one of the first operation and the second operation is selected also based on whether an operation that has been selected for another atomic write operation that is currently being carried out is the first operation or the second operation.

20. The method according to claim 19, wherein

when the atomic write command is for the third namespace, said one of the first operation and the second operation is selected also based on a probability that said another atomic write operation is cancelled before completion.