CONTROLLER-BASED MEMORY SCRUB FOR DRAMS WITH INTERNAL ERROR-CORRECTING CODE (ECC) BITS CONTEMPORANEOUSLY DURING AUTO REFRESH OR BY USING MASKED WRITE COMMANDS

• US 20170161143A1
• Filed: 12/08/2015
• Published: 06/08/2017
• Est. Priority Date: 12/08/2015
• Status: Active Grant

• Current Assignee: NVIDIA Corporation
• Original Assignee: NVIDIA Corporation
• Inventors: REED, David, GUPTA, Alok
• Granted Patent: US 10,049,006 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/106 Correcting systematically all correctable errors, i.e. scrubbing
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 3/0619 in relation to data integrity, e.g. data losses, bit errors
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 11/40615 Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
• CPC Class Codes: G11C 11/4082 Address Buffers; level conversion circuits
• CPC Class Codes: G11C 11/4087 Address decoders, e.g. bit - or word line decoders; Multiple line decoders
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 2029/0411 Online error correction
• CPC Class Codes: G11C 2029/4402 Internal storage of test result, quality data, chip identification, repair information
• CPC Class Codes: G11C 2211/4062 Parity or ECC in refresh operations
• CPC Class Codes: G11C 29/04 Detection or location of defective memory elements , e.g. cell constructio details, timing of test signals
• CPC Class Codes: G11C 7/02 with means for avoiding parasitic signals

Abstract

A method for updating a DRAM memory array is disclosed. The method comprises: a) transitioning the DRAM memory array from an idle state to a refresh state in accordance with a command from a memory controller; b) initiating a refresh on the DRAM memory array using DRAM internal control circuitry by activating a row of data into an associated sense amplifier buffer; and c) during the refresh, performing an ERR Correction Code (ECC) scrub operation of selected bits in the activated row of the DRAM memory array.

Claims

1. A method for updating a DRAM memory array, said method comprising:

a) transitioning the DRAM memory array from an idle state to a refresh state in accordance with a command from a memory controller;

b) initiating a refresh on the DRAM memory array using DRAM internal control circuitry by activating a row of data into an associated sense amplifier buffer;

c) during the refresh, performing an Error Correction Code (ECC) scrub operation of selected bits in the activated row of the DRAM memory array, wherein the ECC scrub operation comprises performing a virtual read and write operation; and

d) updating a refresh column counter.

2. The method of claim 1, further comprising:

d) updating the refresh column counter to select a different set of bits from the selected bits of the activated row from a sense amplifier buffer of the DRAM memory array for a subsequent ECC scrub operation.

3. The method of claim 2, further comprising:

repeating the c) and d) to select and perform an ECC scrub of subsequent bits in the activated row.

4. The method of claim 3, further comprising:

repeating the b), c) and d) for subsequent refresh operations to perform an ECC scrub over all columns for all rows of the DRAM memory array.

5. The method of claim 2, wherein the virtual read and write operation is operable to re-circulate selected data bits through an ECC repair module and store corrected data from the ECC repair module back in the sense amplifier buffer.

6. The method of claim 2, further comprising:

performing an ECC scrub operation for remaining bits over a plurality of rows in the DRAM memory array during subsequent memory controller initiated transitions to the refresh state.

7. The method of claim 1, wherein the refresh state is part of an all bank refresh.

8. The method of claim 4, further comprising:

incrementing a bank counter to address a different portion of the DRAM memory array.

9. The method of claim 1, wherein the refresh state is part of a per bank refresh.

10. The method of claim 1, wherein the performing an ECC scrub further comprises:

reading in the selected bits and corresponding ECC bits;

checking the selected bits to determine if they are correct using the corresponding ECC bits;

correcting the selected bits if the ECC bits indicate an error;

re-computing the ECC bits for the selected bits; and

writing corrected data and ECC bits back into a sense amplifier buffer of the DRAM memory array.

11. The method of claim 10, wherein an address of any detected error is stored in a temporary buffer or register.

12. A method for updating a DRAM memory array, said method comprising:

a) transitioning the DRAM memory array from an idle state to a refresh state in accordance with a command from a memory controller;

b) initiating a refresh on the DRAM memory array using DRAM internal control circuitry by activating a plurality of rows of data into associated sense amplifier buffers;

c) during the refresh, performing an Error Correction Code (ECC) scrub operation of selected bits in the plurality of activated rows of the DRAM memory array, wherein the ECC scrub operation comprises performing a virtual read and write operation; and

d) updating a refresh column counter.

13. The method of claim 12, wherein updating the refresh column counter comprises:

selecting a different set of bits from the selected bits of the plurality of activated rows from the associated sense amplifier buffers of the DRAM memory array for a subsequent ECC scrub operation.

14. The method of claim 13, further comprising:

repeating the c) and d) to select and perform an ECC scrub of subsequent bits in the plurality of activated rows.

15. The method of claim 14, further comprising:

repeating the b), c) and d) for subsequent refresh operations to perform an ECC scrub over all columns for all rows of the DRAM memory array.

16. The method of claim 13, wherein the virtual read and write operation is operable to re-circulate selected data bits through associated ECC repair modules and store corrected data from the associated ECC repair modules back in the associated sense amplifier buffers.

17. The method of claim 12, wherein the refresh state is part of an all bank refresh.

18. The method of claim 12, wherein the refresh state is part of a per bank refresh.

19. The method of claim 15, further comprising:

incrementing a bank counter to address a different portion of the DRAM memory array.

20. The method of claim 12, wherein the performing an ECC scrub further comprises:

reading in the selected bits and corresponding ECC bits;

checking the selected bits to determine if they are correct using the corresponding ECC bits;

correcting the selected bits if the ECC bits indicate an error;

re-computing the ECC bits for the selected bits; and

writing corrected data and ECC bits back into a sense amplifier buffer of the DRAM memory array.

21. An apparatus for updating a DRAM memory array, said apparatus comprising:

the DRAM memory array, wherein the DRAM memory array is configured to;

a) transition the DRAM memory array to a refresh state from an idle state in accordance with a command from a memory controller;

b) initiate a refresh on the DRAM memory array using DRAM internal control circuitry by activating a row of data into an associated sense amplifier buffer;

c) during the refresh, performing an Error Correction Code (ECC) scrub operation of selected bits in an activated row of the DRAM memory array wherein the ECC scrub operation comprises performing a virtual read and write operation; and

d) updating a refresh column counter to select a different set of bits from the selected bits of the plurality of activated rows from the associated sense amplifier buffers of the DRAM memory array for a subsequent ECC scrub operation.

23. The method of claim 21, wherein the Error Correction Code (ECC) scrub operation further comprises:

reading the selected bits and ECC bits that correspond to the selected bits;

determining if the selected bits include an error using the ECC bits;

correcting the selected bits if the selected bits are determined to include an error;

writing the corrected selected bits and ECC bits back to the DRAM memory array.

22. A method for updating a DRAM memory array, comprising:

a) initiating a null partial write to a DRAM memory array; and

b) performing an Error Correction Code (ECC) scrub operation of selected bits in an active column of the DRAM memory array.