PROCESSOR WITH PROGRAMMABLE PREFETCHER

• US 20170161195A1
• Filed: 10/28/2016
• Published: 06/08/2017
• Est. Priority Date: 12/08/2015
• Status: Active Grant

• Current Assignee: Via Alliance Semiconductor Co., Ltd.
• Original Assignee: Via Alliance Semiconductor Co., Ltd.
• Inventors: HOOKER, RODNEY E., REED, DOUGLAS R., HENRY, G. GLENN, PARKS, TERRY
• Granted Patent: US 10,268,586 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0855 Overlapped cache accessing, e.g. pipeline G06F12/0846 takes precedence
• CPC Class Codes: G06F 12/0862 with prefetch
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 2212/452 Instruction code
• CPC Class Codes: G06F 2212/602 Details relating to cache prefetching
• CPC Class Codes: G06F 2212/6022 Using a prefetch buffer or dedicated prefetch cache
• CPC Class Codes: G06F 2212/6028 Prefetching based on hints or prefetch instructions
• CPC Class Codes: G06F 9/30047 Prefetch instructions; cache control instructions
• CPC Class Codes: G06F 9/3802 Instruction prefetching
• CPC Class Codes: G06F 9/3814 Implementation provisions of instruction buffers, e.g. prefetch buffer; banks
• CPC Class Codes: G06F 9/383 Operand prefetching cache prefetching G06F12/0862
• CPC Class Codes: G06F 9/3867 using instruction pipelines

Abstract

A processor including a programmable prefetcher for prefetching information from an external memory. The programmable prefetcher includes a load monitor, a programmable prefetch engine, and a prefetch requester. The load monitor tracks load requests issued by the processor to retrieve information from the external memory. The programmable prefetch engine is configured to be programmed by at least one prefetch program to operate as a programmed prefetcher, such that during operation of the processor, the programmed prefetcher generates at least one prefetch address based on the load requests issued by the processor. The requester uses each generated prefetch address to prefetch information from the external memory. A prefetch memory may store one or more prefetch programs and a prefetch programmer may be included to select from among stored prefetch programs to program the prefetcher based on an executing process. Each prefetch program may be configured according to a prefetch definition.

Claims

1. A processor, comprising:

a programmable prefetcher for prefetching information from an external memory, comprising;

a load monitor that tracks a plurality of load requests issued by the processor to retrieve information from the external memory;

a programmable prefetch engine that is configured to be programmed by at least one prefetch program to operate as a programmed prefetcher, wherein during operation of the processor, said programmed prefetcher generates at least one prefetch address based on said plurality of load requests; and

a prefetch requester that submits said at least one prefetch address to prefetch information from the external memory.

2. The processor of claim 1, further comprising a prefetch memory for storing said at least one prefetch program.

3. The processor of claim 2, wherein said prefetch memory comprises a random-access memory that stores said at least one prefetch program retrieved from the external memory.

4. The processor of claim 3, wherein the processor is responsive to a write command that commands the processor to write said at least one prefetch program from said external memory into said random-access memory.

5. The processor of claim 2, further comprising a prefetch programmer that programs said programmable prefetch engine using said at least one prefetch program stored in said prefetch memory.

6. The processor of claim 5, wherein said prefetch memory comprises a read only memory that stores at least one predetermined prefetch program for programming said programmable prefetch engine to operate according to a predetermined prefetch definition.

7. The processor of claim 6, wherein said at least one predetermined prefetch program comprises a default prefetch program, and wherein said prefetch programmer uses said default prefetch program to program said programmable prefetch engine upon startup of the processor.

8. The processor of claim 5, wherein the processor is responsive to a configure command which causes said prefetch programmer to program said programmable prefetch engine with a specified one of a plurality of prefetch programs stored in said prefetch memory.

9. The processor of claim 2, further comprising a configuration map that maps each of a plurality of different processes with a corresponding one of a plurality of prefetch programs stored in said prefetch memory.

10. The processor of claim 1, wherein said programmable prefetch engine comprises a plurality of programmable logic elements and a plurality of programmable interconnectors.

11. The processor of claim 10, wherein said plurality of programmable logic elements and said plurality of programmable interconnectors are subdivided into a plurality of substantially identical programmable sections, further comprising a prefetch programmer that allocates a number of said programmable sections and that programs said allocated number of said programmable sections with one of said at least one prefetch program to configure said programmed prefetcher.

12. The processor of claim 10, wherein said plurality of programmable logic elements comprises a plurality of programmable lookup tables.

13. The processor of claim 10, wherein said plurality of programmable logic elements comprises a plurality of adders, a plurality of multiplexers, and a plurality of registers.

14. The processor of claim 1, wherein said programmable prefetch engine comprises a programmable memory and wherein said at least one prefetch program comprises a bitstream that is scanned into said programmable memory of said programmable prefetch engine.

15. The processor of claim 1, wherein said programmable prefetch engine is programmed with a plurality of prefetch programs, further comprising a prefetch programmer that enables at least one of said plurality of prefetch programs at a time during operation of the processor.

16. The processor of claim 1, further comprising a cache that receives said plurality of load requests issued by the processor, and that requests and stores corresponding cache lines from said external memory.

17. The processor core of claim 16, wherein said cache comprises a unified cache that receives code and data load requests.

18. A method of programmable prefetching, comprising:

programming a programmable prefetcher of a processor with at least one prefetch program to operate as a programmed prefetcher during operation of the processor for prefetching information from an external memory;

tracking a plurality of load requests issued by the processor to retrieve information from the external memory;

generating, by the programmable prefetcher, at least one prefetch address based on the plurality of load requests; and

submitting the at least one prefetch address to a request queue for requesting information from the external memory.

19. The method of claim 18, further comprising storing the at least one prefetch program in a prefetch memory of the processor.

20. The method of claim 19, further comprising executing, by the processor, a write command that commands the processor to write the at least one prefetch program from the external memory into the prefetch memory which comprises a random-access memory.

21. The method of claim 19, further comprising providing a prefetch programmer within the processor that programs the programmable prefetch engine with the at least one prefetch program stored in the prefetch memory.

22. The method of claim 19, further comprising executing, by the processor, a configure command that commands the processor to program the programmable prefetch engine with a selected one of at least one prefetch program stored in the prefetch memory.

23. The method of claim 19, further comprising storing in the processor a configuration map that maps each of a plurality of different processes with a corresponding one of a plurality of prefetch programs stored in the prefetch memory.

24. The method of claim 18, further comprising providing the programmable prefetch engine in the processor as a plurality of programmable logic elements and a plurality of programmable interconnectors.

25. The method of claim 24, further comprising:

subdividing the plurality of programmable logic elements and the plurality of programmable interconnectors into a plurality of substantially identical programmable sections;

allocating a number of the programmable sections to configure the programmed prefetcher according to the at least one prefetch program; and

wherein said programming a programmable prefetcher comprises programming the allocated number of the programmable sections with the at least one prefetch program.

26. The method of claim 18, further comprising:

providing the programmable prefetch engine as a programmable memory; and

wherein said programming a programmable prefetcher comprises scanning the at least one prefetch program as a bitstream into the programmable memory of the programmable prefetch engine.

27. The method of claim 18, wherein said programming a programmable prefetcher comprises programming the programmable prefetcher with a plurality of prefetch programs, further comprising enabling at least one of the plurality of prefetch programs at a time during operation of the processor.