ELECTRONIC SYSTEM WITH MEMORY MANAGEMENT MECHANISM AND METHOD OF OPERATION THEREOF

• US 20170161201A1
• Filed: 06/06/2016
• Published: 06/08/2017
• Est. Priority Date: 12/03/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Malladi, Krishna, Kang, Uksong, Zheng, Hongzhong
• Granted Patent: US 9,934,154 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0811 with multilevel cache hierarchies
• CPC Class Codes: G06F 12/0868 Data transfer between cache memory and other subsystems, e.g. storage devices or host systems
• CPC Class Codes: G06F 12/0897 with two or more cache hierarchy levels with multilevel cache hierarchies G06F12/0811
• CPC Class Codes: G06F 13/1673 using buffers
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/60 Details of cache memory

Abstract

An electronic system includes: a processor configured to access operation data; a local cache memory, coupled to the processor, configured to store a limited amount of the operation data; a memory controller, coupled to the local cache memory, configured to maintain a flow of the operation data; and a memory subsystem, coupled to the memory controller, including: a first tier memory configured to store the operation data, with critical timing, by a fast control bus, and a second tier memory configured to store the operation data with non-critical timing, by a reduced performance control bus.

Claims

1. An electronic system comprising:

a processor configured to access operation data;

a high speed local memory, coupled to the processor, configured to store a limited amount of the operation data;

a memory controller, coupled to a buffering cache memory, configured to maintain a flow of the operation data; and

a memory subsystem, coupled to the memory controller, including;

a first tier memory configured to store the operation data, with critical timing, by a fast control bus, and

a second tier memory configured to store the operation data with non-critical timing, by a reduced performance control bus.

2. The system as claimed in claim 1 wherein the second tier memory provides more capacity and longer latency than the first tier memory.

3. The system as claimed in claim 1 wherein the second tier memory includes a modified local bit-line sense amplifier having a bit-line feedback circuit.

4. The system as claimed in claim 1 wherein the second tier memory includes a global word-line driver coupled to a storage cell array.

5. The system as claimed in claim 1 wherein the second tier memory includes a storage cell array with a poly-silicon interconnect for a bit-line (BL).

6. The system as claimed in claim 1 wherein the memory subsystem'"'"'s first tier memory is a low latency device, including address line amplifiers and local sub-word-line drivers, and the second tier memory is a higher capacity device that does not include the address line amplifiers and the local sub-word-line drivers.

7. The system as claimed in claim 1 wherein the second tier memory includes a modified local bit-line sense amplifier with a bit-line precharge circuit.

8. The system as claimed in claim 1 wherein the second tier memory includes a global word-line driver configured to couple global word-lines directly to array segments.

9. The system as claimed in claim 1 wherein the second tier memory includes a greater number of array segments than the first tier memory.

10. The system as claimed in claim 1 wherein the second tier memory includes a modified local bit-line sense amplifier including a control line set_high and a control line set_low coupled to a bit-line feedback circuit.

11. The system as claimed in claim 1 wherein the second tier memory includes 30-50% greater capacity than the first tier memory due to a global word-line driver, an optimized local bit-line sense amplifier, and poly-silicon routing for a bit-line (BL).

12. The system as claimed in claim 1 wherein the second tier memory includes additional capacity in a storage cell array and coupling a poly-silicon interconnect for a bit-line (BL).

13. The system as claimed in claim 1 wherein the second tier memory includes an optimized local bit-line sense amplifier with a narrower transistor than a local bit-line sense amplifier of the first tier memory.

14. The system as claimed in claim 1 wherein the memory subsystem includes the first tier memory and the second tier memory mounted in a module.

15. The system as claimed in claim 1 wherein the memory controller provides a low latency access to the first tier memory and a high latency access to the second tier memory.