HOST CONTROLLER OF HIGH-SPEED DATA INTERFACE
First Claim
1. A host controller of high-speed data interface, comprising:
- a logical physical layer and a plurality of electrical physical layers, wherein the logical physical layer provides a plurality of groups of low-speed data, each of the electrical physical layers converts one group of the low-speed data to high-speed data and transmit the high-speed data to one of a plurality of external devices, and each of the electrical physical layers operates according to one of a plurality of clock signals;
a multiplexer, receiving the plurality of clock signals corresponding to the plurality of electrical physical layers to output a common clock signal for the logical physical layer to provide the plurality of groups of low-speed data based on the common clock signal; and
a clock-domain-crossing transmitter, coupled between the logical physical layer and the plurality of electrical physical layers, and using the common clock signal to retrieve the plurality of groups of low-speed data provided from the logical physical layer,wherein, with respect to each of the external devices, the clock-domain-crossing transmitter uses the one of the plurality of clock signals corresponding to the electrical physical layer connected to the external device to output the corresponding group of low-speed data to the electrical physical layer connected to the external device.
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Accused Products
Abstract
A host controller with suppressed data jitter is shown, which uses a logical physical layer (LPHY) to provide groups of low-speed data, uses a clock-domain-crossing transmitter (TXCDC) to transmit the groups of the low-speed data to the corresponding electrical physical layers (EPHYs), uses the EPHYs to convert the groups of the low-speed data to high-speed data and transmit the high-speed data to the corresponding external devices, and further has a multiplexer. Each EPHY corresponds to one clock signal and operates accordingly. The multiplexer receives the clock signals of the EPHYs to output a common clock signal for the LPHY to provide the groups of low-speed data and for the TXCDC to retrieve the groups of low-speed data. With respect to each of the external devices, the TXCDC uses the clock signal corresponding to the corresponding EPHY to output the corresponding group of low-speed data to the corresponding EPHY.
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Citations
19 Claims
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1. A host controller of high-speed data interface, comprising:
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a logical physical layer and a plurality of electrical physical layers, wherein the logical physical layer provides a plurality of groups of low-speed data, each of the electrical physical layers converts one group of the low-speed data to high-speed data and transmit the high-speed data to one of a plurality of external devices, and each of the electrical physical layers operates according to one of a plurality of clock signals; a multiplexer, receiving the plurality of clock signals corresponding to the plurality of electrical physical layers to output a common clock signal for the logical physical layer to provide the plurality of groups of low-speed data based on the common clock signal; and a clock-domain-crossing transmitter, coupled between the logical physical layer and the plurality of electrical physical layers, and using the common clock signal to retrieve the plurality of groups of low-speed data provided from the logical physical layer, wherein, with respect to each of the external devices, the clock-domain-crossing transmitter uses the one of the plurality of clock signals corresponding to the electrical physical layer connected to the external device to output the corresponding group of low-speed data to the electrical physical layer connected to the external device. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A host controller of high-speed data interface, comprising:
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a logical physical layer and an electrical physical layer, wherein the logical physical layer provides first low-speed data, the electrical physical layer converts the first low-speed data to first high-speed data and transmits the first high-speed data to a first external device, the electrical physical layer operates according to a clock signal, and the clock signal is further transmitted to the logical physical layer to operate the logical physical layer to provide the first low-speed data; and a clock-domain-crossing transmitter, coupled between the logical physical layer and the electrical physical layers, using an LPHY side clock signal to retrieve the first low-speed data that the logical physical layer provides for the first external device, and using a EPHY side clock signal to output the first low-speed data to the electrical physical layer. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19)
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Specification