MEMORY DEVICE

• US 20170162257A1
• Filed: 03/09/2016
• Published: 06/08/2017
• Est. Priority Date: 12/04/2015
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: KATO, Koji, KUROSAWA, Tomonori, NAKANO, Takeshi, KOBAYASHI, Tsukasa
• Granted Patent: US 10,096,356 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits

Abstract

According to one embodiment, a memory device includes a first memory cell; a second memory cell; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a first word line connected to the first memory cell and the second memory cell; a first circuit configured to control a connection between the first bit line and a first node; and a second circuit configured to control a connection between the second bit line and the first node.

Claims

1. A memory device comprising:

a first memory cell;

a second memory cell;

a first bit line connected to the first memory cell;

a second bit line connected to the second memory cell;

a first word line connected to the first memory cell and the second memory cell;

a first circuit configured to control a connection between the first bit line and a first node; and

a second circuit configured to control a connection between the second bit line and the first node,

wherein, at a time of writing data to the first memory cell, the memory device is configured;

to apply a first voltage to the second bit line,

to apply a second voltage, which is lower than the first voltage, to the first bit line, and

to apply a third voltage, which is higher than the first voltage, to the first word line, and

the memory device is configured, at a time of starting discharge of the first word line to a fourth voltage which is lower than the third voltage, after the third voltage was applied to the first word line, to turn on the first circuit and the second circuit and to apply a fifth voltage, which is higher than the second voltage, to the first node.

2. The memory device according to claim 1, wherein the memory device is configured to apply the first voltage to the first node until a voltage, which is applied to the first word line, varies from the third voltage to the fourth voltage.

3. The memory device according to claim 2, wherein the memory device is configured to vary a potential of the first node from the first voltage to the second voltage, after the voltage, which is applied to the first word line, is varied to the fourth voltage.

4. The memory device according to claim 3, wherein the memory device is configured to vary the potential of the first node from the first voltage to the second voltage, when the first bit line and the second bit line have become equal in potential.

5. The memory device according to claim 1, wherein the fifth voltage is the first voltage, or a sixth voltage at which a select transistor belonging to the same string as the second memory cell is capable of maintaining a cutoff state.

6. The memory device according to claim 1, wherein the memory device is configured to apply the fifth voltage to the first node until a voltage, which is applied to the first word line varies from the third voltage to the fourth voltage, and to apply, thereafter, at a time of discharge from the fourth voltage to the second voltage, a seventh voltage, which is higher than the second voltage and is lower than the first voltage, to the first node.

7. The memory device according to claim 6, wherein the memory device is configured to vary a potential of the first node from the first voltage to the second voltage, after the voltage, which is applied to the first word line, is varied to the fourth voltage.

8. The memory device according to claim 7, wherein the memory device is configured to vary the potential of the first node from the first voltage to the second voltage, when the first bit line and the second bit line have become equal in potential.

9. The memory device according to claim 8, wherein the memory device is configured to determine whether data was written to the first memory cell, after the first node was set to the second voltage.

10. The memory device according to claim 1, wherein the fourth voltage is a voltage which is capable of turning on the first and second memory cells, without erroneous write being executed to the first and second memory cells.

11. A method for controlling a memory device, comprising:

applying, when writing data to a first memory cell which is connected to a first bit line and a first word line, a first voltage to a second bit line at a first timing;

applying a second voltage, which is lower than the first voltage, to the first bit line at the first timing;

applying a third voltage, which is higher than the first voltage, to the first word line at a second timing which is later than the first timing;

applying a fourth voltage, which is lower than the third voltage, to the first word line at a third timing which is later than the second timing;

turning on, at the third timing, a first circuit configured to control a connection between the first bit line and the first node and a second circuit configured to control a connection between the second bit line and the first node; and

applying a fifth voltage, which is higher than the second voltage, to the first node at the third timing.

12. The method according to claim 11, wherein the applying the fifth voltage to the first node includes applying the fifth voltage to the first node until a voltage, which is applied to the first word line, varies from the third voltage to the fourth voltage.

13. The method according to claim 12, further comprising applying the second voltage to the first node, after the voltage, which is applied to the first word line, is varied to the fourth voltage.

14. The method according to claim 13, wherein the applying the second voltage to the first node is executed when the first bit line and the second bit line have become equal in potential.

15. The method according to claim 11, wherein the fifth voltage is the first voltage, or a sixth voltage at which a select transistor belonging to the same string as the second memory cell is capable of maintaining a cutoff state.

16. The method according to claim 11, further comprising:

applying the fifth voltage to the first node until a voltage, which is applied to the first word line, varies from the third voltage to the fourth voltage; and

applying, thereafter, at a time of discharge from the fourth voltage to the second voltage, the fifth voltage, which is higher than the second voltage and is lower than the first voltage, to the first node.

17. The method according to claim 16, further comprising applying the second voltage to the first node, after the voltage, which is applied to the first word line, is varied to the fourth voltage.

18. The method according to claim 17, wherein the applying the second voltage to the first node is executed when the first bit line and the second bit line have become equal in potential.

19. The method according to claim 18, further comprising determining whether data was written to the first memory cell, after the first node was set to the second voltage.

20. The method according to claim 11, wherein the fourth voltage is a voltage which is capable of turning on the first memory cell, without erroneous write being executed to the first memory cell.