LOW-DAMAGE ETCHING METHOD FOR III-NITRIDE

• US 20170162398A1
• Filed: 03/03/2016
• Published: 06/08/2017
• Est. Priority Date: 12/02/2015
• Status: Abandoned Application

• Current Assignee: Institute of Microelectronics Chinese Academy of Sciences (Chinese Academy of Sciences)
• Original Assignee: Institute of Microelectronics Chinese Academy of Sciences (Chinese Academy of Sciences)
• Inventors: LIU, Xinyu, HUANG, Sen, WANG, Xinhua, WEI, Ke
• Application Number:
  US15/060,406
• Publication Number:
  US 20170162398A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/30621 Vapour phase etching
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/417 carrying the current to be rectified, amplified or switched
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7786 with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT

Abstract

A low-damage etching method for a III-Nitride structure is disclosed. The method comprises: forming an etching mask on the III-Nitride structure, which is formed on a substrate; and etching the III-Nitride with the etching mask, wherein a temperature of the substrate changes dynamically or is kept at a constant temperature point between 200° C. and 700° C. during the etching.

Claims

1. A low-damage etching method for a III-Nitride structure, comprising:

forming an etching mask on the III-Nitride structure, which is formed on a substrate;

etching the III-Nitride with the etching mask, and

increasing a temperature of the substrate stepwisely, wherein for a time interval that corresponds to each temperature step of the substrate, the etching is restricted to a period that occurs earlier than or later than the time interval.

2. The method according to claim 1, wherein during the etching,

the substrate temperature increases step-wisely from 200°

C. to 700°

C.

3. The method according to claim 1, wherein the III-Nitride comprises any one selected from a group consisting of AlN, GaN, InN, or a combination of AlN, GaN, and InN.

4. The method according to claim 1, wherein the etching mask comprises a dielectric or metal material.

5. The method according to claim 4, wherein:

the dielectric material comprises SiO₂ or SiN_x; and

the metal material comprises any one selected from a group consisting of Ni, Ti, Pt, or TiN, or any combination thereof.

6. The method according to claim 1, suitable for use in III-Nitride etching in forming a gate recess in a transistor, a pre-ohmic recess, or a mesa isolation.

7. The method according to claim 1, wherein the etching is carried out using any one selected from a group consisting of Cl-base plasma, a combination of F-base plasma and Cl-base plasma, or a combination of Ar-base plasma and Cl-base plasma.

8. The method according to claim 7, wherein the Cl-base plasma comprises any one selected from a group consisting of Cl₂, BCl₃, or a combination thereof.

9. The method according to claim 1, wherein the etching comprises inductively coupled plasma dry etching or reactive ion etching, or a combination thereof.