SEMICONDUCTOR DEVICE

• US 20170162500A1
• Filed: 09/07/2016
• Published: 06/08/2017
• Est. Priority Date: 12/03/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: LEE, Chanho, CHUNG, HYUNSOO, PARK, Myeong Soon
• Granted Patent: US 9,960,112 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/4846 Leads on or in insulating or insulated substrates, e.g. metallisation H01L21/4821 takes precedence; metallisation of ceramics in general C04B41/51; printed circuits H05K3/00
• CPC Class Codes: H01L 2224/0401 Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
• CPC Class Codes: H01L 2224/05567 the external layer being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13021 the bump connector being disposed in a recess of the surface
• CPC Class Codes: H01L 2224/13022 the bump connector being at least partially embedded in the surface
• CPC Class Codes: H01L 2224/13082 Two-layer arrangements
• CPC Class Codes: H01L 2224/13109 Indium [In] as principal constituent
• CPC Class Codes: H01L 2224/13111 Tin [Sn] as principal constituent
• CPC Class Codes: H01L 2224/13113 Bismuth [Bi] as principal constituent
• CPC Class Codes: H01L 2224/1312 Antimony [Sb] as principal constituent
• CPC Class Codes: H01L 2224/13139 Silver [Ag] as principal constituent
• CPC Class Codes: H01L 2224/13147 Copper [Cu] as principal constituent
• CPC Class Codes: H01L 2224/13155 Nickel [Ni] as principal constituent
• CPC Class Codes: H01L 2224/1403 Bump connectors having different sizes, e.g. different diameters, heights or widths
• CPC Class Codes: H01L 2224/14104 relative to the bonding areas, e.g. bond pads, of the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/14166 Covering only the central area of the surface to be connected, i.e. central arrangements
• CPC Class Codes: H01L 2224/16238 the bump connector connecting to a bonding area protruding from the surface of the item
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/14 : of a plurality of bump connectors
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/014 : Solder alloys
• CPC Class Codes: H01L 2924/351 : Thermal stress

Abstract

A semiconductor device comprising: a substrate; a decoupling capacitor disposed on the substrate; a first connection pad vertically overlapping with the decoupling capacitor; a passivation layer exposing a portion of the first connection pad; and a first solder bump disposed on the first connection pad and covering a portion of a top surface of the passivation layer.

Claims

1. A semiconductor device comprising:

a substrate;

a decoupling capacitor disposed on the substrate;

a first connection pad vertically overlapping with the decoupling capacitor;

a passivation layer exposing a portion of the first connection pad; and

a first solder bump disposed on the first connection pad and covering a portion of a top surface of the passivation layer.

2. The semiconductor device of claim 1, further comprising:

a circuit formed on the substrate;

wherein the first solder bump and the first connection pad are part of a power or ground path electrically connected to the circuit.

3. The semiconductor device of claim 1, wherein:

the passivation layer has a first opening exposing a portion of a top surface of the first connection pad; and

the first solder bump substantially completely covers the exposed portion of the top surface of the first connection pad.

4. The semiconductor device of claim 3, wherein the first solder bump fills the first opening and extends from the first connection pad over the top surface of the passivation layer.

5. The semiconductor device of claim 3, wherein:

the first opening has a first width along a direction; and

a width of the first solder bump along the direction is greater than the first width.

6. The semiconductor device of claim 1, further comprising:

a second connection pad laterally offset from the decoupling capacitor; and

a second solder bump disposed on the second connection pad.

7. The semiconductor device of claim 6, wherein a width of the first solder bump is greater than a width of the second solder bump.

8. The semiconductor device of claim 7, wherein the second solder bump is vertically offset from any decoupling capacitor formed on the substrate.

9. The semiconductor device of claim 1, wherein the first connection pad is electrically connected to the decoupling capacitor.

10. The semiconductor device of claim 1, wherein:

the first solder bump comprises a pillar and solder; and

the pillar contacts the top surface of the passivation layer.

11. A semiconductor device comprising:

a substrate;

a decoupling capacitor disposed on the substrate;

a first solder bump vertically overlapping with the decoupling capacitor; and

a second solder bump offset from the decoupling capacitor;

wherein a width of the first solder bump is greater than a width of the second solder bump.

12. The semiconductor device of claim 11, further comprising:

a circuit disposed on the substrate;

wherein;

the first solder bump is part of a power or ground path electrically connected to the circuit; and

the second solder bump is part of a signal path electrically connected to the circuit.

13. The semiconductor device of claim 11, wherein:

the substrate includes a cell region and a peripheral circuit region;

the decoupling capacitor is formed in the peripheral circuit region; and

the semiconductor device further comprises a memory element disposed on the substrate in the cell region.

14. The semiconductor device of claim 11, further comprising:

a passivation layer having a first opening exposing a first connection pad;

wherein the first solder bump fills the first opening and is in contact with the passivation layer.

15. The semiconductor device of claim 14, wherein:

the first opening has a first width along a direction;

the first solder bump extends from the first connection pad over a top surface of the passivation layer; and

a width of the first solder bump along the direction is greater than the first width.

16. The semiconductor device of claim 14, wherein:

the passivation layer includes a second opening exposing a second connection pad; and

the second solder bump is provided in the second opening on the second connection pad and is spaced apart from the passivation layer.

17. The semiconductor device of claim 11, wherein the first solder bump and the decoupling capacitor are electrically connected to each other through metal interconnections.

18. A semiconductor package, comprising:

a package substrate;

a semiconductor chip including a decoupling capacitor and a passivation layer;

a plurality of solder bumps electrically connecting the semiconductor chip to the package substrate;

wherein;

a first solder bump of the solder bumps is vertically aligned with the decoupling capacitor and extends over the passivation layer; and

a second solder bump of the solder bumps is spaced apart from the passivation layer.

19. The semiconductor package of claim 18, wherein the second solder bump is vertically offset from any decoupling capacitor of the semiconductor chip.

20. The semiconductor package of claim 18, wherein a width of the first solder bump is greater than a width of the second solder bump.