SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE

• US 20170162563A1
• Filed: 06/08/2015
• Published: 06/08/2017
• Est. Priority Date: 08/06/2014
• Status: Active Grant

• Current Assignee: DENSO Corporation
• Original Assignee: Toyota Jidosha Kabushiki Kaisha (Toyota Motor Corporation)
• Inventors: OKAWARA, Jun, KAMEYAMA, Satoru, IWASAKI, Shinya, MISUMI, Tadashi
• Granted Patent: US 9,966,372 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/768 Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
• CPC Class Codes: H01L 21/8249 Bipolar and MOS technology
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 27/0716 in combination with vertical bipolar transistors and diodes, or capacitors, or resistors
• CPC Class Codes: H01L 27/0727 in combination with diodes, or capacitors or resistors
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/417 carrying the current to be rectified, amplified or switched
• CPC Class Codes: H01L 29/41708 Emitter or collector electrodes for bipolar transistors
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/7804 the other device being a pn-junction diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/8613 Mesa PN junction diodes
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A semiconductor device includes: a plurality of trenches provided in an upper surface of a semiconductor substrate; trench electrodes each provided in a corresponding one of the trenches; a first semiconductor layer of a first conductivity type provided in a first range interposed between adjacent ones of the trenches; a second semiconductor layer of a second conductivity type; a third semiconductor layer of the first conductivity type; an interlayer insulation film provided on the upper surface of the semiconductor substrate and including a plurality of contact holes; a first conductor layer provided in each of the contact holes; and a surface electrode provided on the interlayer insulation film and connected to each of the first conductor layers.

Claims

1. A semiconductor device comprising:

a semiconductor substrate;

a plurality of trenches provided in an upper surface of the semiconductor substrate;

trench insulating films each covering a corresponding one of inner surfaces of the trenches;

trench electrodes each provided in a corresponding one of the trenches and insulated from the semiconductor substrate by the trench insulating film;

a first semiconductor layer of a first conductivity type provided in the semiconductor substrate in a first range interposed between adjacent two of the trenches, exposed on the upper surface of the semiconductor substrate, and being in contact with the trench insulating film;

a second semiconductor layer of a second conductivity type provided in the semiconductor substrate in the first range, a part of the second semiconductor layer being exposed on the upper surface of the semiconductor substrate, and the second semiconductor layer being in contact with the trench insulating film on a lower side of the first semiconductor layer;

a third semiconductor layer of the first conductivity type provided in the semiconductor substrate, provided on a lower side of the second semiconductor layer, separated from the first semiconductor layer by the second semiconductor layer, and being in contact with the trench insulating film on the lower side of the second semiconductor layer;

an interlayer insulating film provided on the upper surface of the semiconductor substrate and on the trench electrodes, and comprising a plurality of contact holes provided in the first range;

first conductor layers each provided in a corresponding one of the contact holes and connected to at least one of the first semiconductor layer and the second semiconductor layer; and

a surface electrode provided on the first conductor layers and the interlayer insulating film and connected to each of the first conductor layers,

wherein

each of the contact holes extends parallel to the trenches, and

the contact holes are arranged in a width direction of the first range with intervals.

2. The semiconductor device of claim 1, further comprising:

a fourth semiconductor layer of the second conductivity type provided in the semiconductor substrate in a second range different from the first range and interposed between adjacent two of the trenches, and exposed on the upper surface of the semiconductor substrate; and

a second conductor layer,

wherein

a part of the third semiconductor layer is provided on a lower side of the fourth semiconductor layer and being in contact with the fourth semiconductor layer,

the interlayer insulating film comprises a contact hole provided in the second range,

the second conductor layer is provided in the contact hole in the second range and connected to the fourth semiconductor layer,

a part of the surface electrode is provided on the second conductor layer and connected to the second conductor layer, and

a value obtained by dividing a contact area of the plurality of the first conductor layers with respect to the semiconductor substrate by an area of the first range is greater than a value obtained by dividing a contact area of the second conductor layer with respect to the semiconductor substrate by an area of the second range.

3. The semiconductor device of claim 1, wherein Young'"'"'s modulus of the first conductor layers is higher than Young'"'"'s modulus of the surface electrode.

4. The semiconductor device of claim 1, wherein the first conductor layers are constituted of a material formable by CVD, plating, or sputtering.

5. The semiconductor device of claim 1, wherein the first conductor layers are constituted of a material comprising any of W, Al, and Cu.

6. The semiconductor device of claim 1, wherein a width of the interlayer insulating film on each of the trench electrodes is wider than a width of the interlayer insulating film interposed between the plurality of the contact holes in the first range.

7. A method of manufacturing a semiconductor device from a production wafer that comprises:

a semiconductor substrate comprising a plurality of trenches provided in an upper surface of the semiconductor substrate;

trench insulating films each covering a corresponding one of inner surfaces of the trenches; and

trench electrodes each provided in a corresponding one of trenches and insulated from the semiconductor substrate by the trench insulating film,

the semiconductor substrate comprises;

a first semiconductor layer of a first conductivity type provided in a range interposed between adjacent two of the trenches, exposed on the upper surface of the semiconductor substrate, and being in contact with the trench insulating film;

a second semiconductor layer of a second conductivity type provided in the range, a part of the second semiconductor layer being exposed on the upper surface of the semiconductor substrate, and the second semiconductor layer being in contact with the trench insulating film on a lower side of the first semiconductor layer; and

a third semiconductor layer of the first conductivity type provided on a lower side of the second semiconductor layer, separated from the first semiconductor layer by the second semiconductor layer, and being in contact with the trench insulating film on the lower side of the second semiconductor layer;

the method comprising;

forming an interlayer insulating film on an upper surface of the production wafer;

forming a plurality of contact holes in the interlayer insulating film in the range, each of the contact holes extending parallel to the trenches, and the contact holes being arranged in a width direction of the range with intervals;

growing a conductor layer in the contact holes and on the interlayer insulating film;

etching the conductor layer on the interlayer insulating film so that the conductor layer remains in the contact holes; and

forming a surface electrode on the conductor layer and the interlayer insulating film after the etching.