Si RECESS METHOD IN HKMG REPLACEMENT GATE TECHNOLOGY
First Claim
1. An integrated circuit comprising:
- a substrate including a periphery region having a first substrate surface and a memory cell region having a second substrate surface, wherein the second substrate surface is recessed within the substrate relative to the first substrate surface;
a high-k metal gate (HKMG) transistor disposed on the first substrate surface and including a gate electrode; and
two neighboring flash memory cells formed on the second substrate surface and including a pair of flash memory cell control gates, wherein a top surface of the gate electrode is co-planar with top surfaces of the pair of flash memory cell control gates.
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Accused Products
Abstract
The present disclosure relates to an integrated circuit (IC). The IC includes a substrate, which includes a periphery region having a first substrate surface and a memory cell region having a second substrate surface. The second substrate surface is recessed within the substrate relative to the first substrate surface. A high k metal gate (HKMG) transistor is disposed on the first substrate surface and includes a HKMG gate. Two neighboring flash memory cells are disposed on the second substrate surface and include a pair of flash memory cell control gates. Top surfaces of the HKMG gate and flash memory cell control gates are co-planar.
12 Citations
20 Claims
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1. An integrated circuit comprising:
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a substrate including a periphery region having a first substrate surface and a memory cell region having a second substrate surface, wherein the second substrate surface is recessed within the substrate relative to the first substrate surface; a high-k metal gate (HKMG) transistor disposed on the first substrate surface and including a gate electrode; and two neighboring flash memory cells formed on the second substrate surface and including a pair of flash memory cell control gates, wherein a top surface of the gate electrode is co-planar with top surfaces of the pair of flash memory cell control gates. - View Dependent Claims (2, 3, 4, 5, 6)
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7. An integrated circuit, comprising:
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a substrate including a periphery region having a first substrate surface and a memory cell region having a second substrate surface, wherein the second substrate surface is recessed within the substrate relative to the first substrate surface; a logic transistor disposed on the first substrate surface and including a logic gate electrode separated from the first surface by a logic gate dielectric; and a memory cell disposed on the second substrate surface and including a memory gate electrode separated from the second surface by a memory gate dielectric, wherein a top surface of the logic gate electrode is co-planar with a top surface of the memory gate electrode. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15)
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16. An integrated circuit, comprising:
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a substrate including a first region having a first substrate surface and a second region having a second substrate surface, wherein the second substrate surface is recessed within the substrate relative to the first substrate surface; a first transistor disposed on the first substrate surface and including a first gate electrode separated from the first surface by a first gate dielectric; and a second transistor disposed on the second substrate surface and including a second gate electrode separated from the second surface by a second gate dielectric, wherein a top surface of the first gate electrode is co-planar with a top surface of the second gate electrode. - View Dependent Claims (17, 18, 19, 20)
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Specification