SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20170162668A1
• Filed: 11/10/2016
• Published: 06/08/2017
• Est. Priority Date: 12/07/2015
• Status: Abandoned Application

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: KIM, SUNG MIN, SHIN, HEON JONG
• Application Number:
  US15/348,040
• Publication Number:
  US 20170162668A1
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/28114 characterised by the sectional shape, e.g. T, inverted-T
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/7851 with the body tied to the substrate

Abstract

A method of manufacturing a semiconductor device includes forming a fin extending in a first direction. A dummy layer is formed including a plurality of semiconductor layers disposed on the fin. Each of the plurality of semiconductor layers have different impurity concentrations from each other. The dummy layer is etched to form a dummy gate electrode.

Claims

1. A method of manufacturing a semiconductor device, comprising:

forming a fin extending in a first direction;

forming a dummy layer including a plurality of semiconductor layers disposed on the fin, wherein each of the plurality of semiconductor layers has different impurity concentrations from each other; and

etching the dummy layer to form a dummy gate electrode.

2. The method of claim 1,

wherein each of the plurality of semiconductor layers has different etching rates from each other with respect to the same etchant according to the different impurity concentrations for each of the semiconductor layers.

3. The method of claim 1,

wherein the impurity concentration of each of the plurality of semiconductor layers increases as it is closer to the fin.

4. The method of claim 3,

wherein an impurity doped in each of the plurality of semiconductor layers is at least one of germanium (Ge), phosphorus (P), and arsenic (As).

5. The method of claim 3,

herein the etching rate of each of the plurality of semiconductor layers increases as the purity concentration increases.

6. The method of claim 3,

wherein the impurity concentration is changed with a gradient in each of the plurality of semiconductor layers.

7. The method of claim 1, wherein the forming the dummy gate electrode comprises forming a concave line along an upper surface and a side wall of the fin between the dummy gate electrode and the fin.

8. The method of claim 7, wherein the forming the dummy gate electrode comprises cleaning the dummy gate electrode with a cleaning solution to trim the concave line.

9. The method of claim 7, wherein the forming the dummy gate electrode comprises oxidizing the surface of the dummy gate electrode, and etching an oxidized surface of the dummy gate electrode.

10. The method of claim 1, wherein the forming the dummy layer comprises forming the dummy layer through a dummy layer deposition process, wherein the dummy layer deposition process includes an impurity injection process of injecting impurities, and wherein the concentration of the impurities injected in the impurity injection process is lowered over time.

11. The method of claim 1, further comprising:

forming a spacer on a side wall of the dummy gate electrode; and

replacing the dummy gate electrode with a gate electrode.

12. A method of manufacturing a semiconductor device, comprising:

forming a fin extending in a first direction;

forming a field insulating film formed along a relatively longer side of the fin and exposing the upper portion of the fin;

forming a dummy layer on the exposed upper portion fin through a dummy layer deposition process;

etching the dummy layer to form a dummy gate electrode including a concave line formed between the dummy layer and the fin;

forming a spacer on the side wall of the dummy gate electrode to fill the concave line; and

replacing the dummy gate electrode with a gate electrode.

13. The method of claim 12, wherein the dummy layer deposition process includes an impurity injection process of injecting impurities, and wherein the concentration of the impurities injected in the impurity injection process is lowered over time.

14. The method of claim 13, wherein the impurities injected in the impurity injection process include at least one of germanium (Ge), phosphorus (P), and arsenic (As).

15. The method of claim 13, wherein the dummy layer includes a plurality of semiconductor layers having different impurity concentrations form each other, and wherein the etching rates of the plurality of semiconductors with respect to the same etchant increase as the impurity concentrations increase.

16. A method of manufacturing a semiconductor device, comprising:

forming a fin on a substrate;

forming a field insulating film formed on first and second side surfaces of the fin;

forming a dummy gate insulating film conformally covering upper surfaces of the field insulating film, the first and second side surfaces of the fin, and an upper surface of the fin;

performing a dummy layer deposition process and an impurity injection process to form a dummy layer including a plurality of semiconductor layers disposed on the fin, wherein each of the plurality of semiconductor layers has different impurity concentrations from each other; and

etching the dummy layer to form a dummy gate electrode.

17. The method of claim 16, wherein the impurity concentration of each of the plurality of semiconductor layers increases as it is closer to the fin.

18. The method of claim 16, wherein an impurity doped in each of the plurality of semiconductor layers is at least one of germanium (Ge), phosphorus (P), and arsenic (As).

19. The method of claim 17, wherein the etching rate of each of the plurality of semiconductor layers increases as the purity concentration increases.

20. The method of claim 17, wherein the impurity concentration is changed with a gradient in each of the plurality of semiconductor layers.