APPARATUS AND METHOD FOR CONTROLLING ASYMMETRIC MODULAR MULTILEVEL CONVERTER

• US 20170163171A1
• Filed: 12/02/2016
• Published: 06/08/2017
• Est. Priority Date: 12/03/2015
• Status: Active Grant

• Current Assignee: Industry Academic Cooperation Foundation
• Original Assignee: Industry Academic Cooperation Foundation, Korea Electrotechnology Research Institute
• Inventors: PARK, Jungwook
• Granted Patent: US 10,044,294 B2
• Time in Patent Office: Days
• CPC Class Codes: H02M 7/483 Converters with outputs that each can have more than two voltages levels
• CPC Class Codes: H02M 7/4835 comprising two or more cells, each including a switchable capacitor, the capacitors having a nominal charge voltage which corresponds to a given fraction of the input voltage, and the capacitors being selectively connected in series to determine the instantaneous output voltage
• CPC Class Codes: H02M 7/537 using semiconductor devices only, e.g. single switched pulse inverters

Abstract

Disclosed is an apparatus and method for controlling an asymmetric modular multilevel converter which allow numerous levels to be expressed according to a combination of modules each using a different voltage, comprising: an asymmetric arm configured with a full bridge and a half bridge; and a control method of controlling each capacitor level of the full bridges and capacitor level of the remaining half bridges to be different from one another by a full bridge structure, wherein each module configuring the asymmetric arm uses a different voltage and an output voltage is expressed by a combination thereof.

Claims

1. An apparatus for controlling an asymmetric modular multilevel converter, comprising:

an asymmetric arm configured with a full bridge and a half bridge; and

a control method of controlling each capacitor level of the full bridge and capacitor level of the remaining half bridge to be different from one another by a full bridge structure,

wherein each module configuring the asymmetric arm uses a different voltage and an output voltage is expressed by a combination thereof.

2. The apparatus of claim 1, wherein:

an upper asymmetric arm and a lower asymmetric arm are connected in series between a V_DC input terminal and a V_AC output terminal to configure a single-phase asymmetric modular multilevel converter; and

three single-phase asymmetric modular multilevel converters are connected by sharing a direct current (DC) bus to configure a three-phase asymmetric modular multilevel converter.

3. The apparatus of claim 1, wherein:

the asymmetric arm is configured with N Modules f configured with the full bridge and K Modules h configured with the half bridge between a V_DC positive (+) input terminal and a V_DC negative (−

) input terminal;

each Module h is responsible for an equally divided voltage; and

a sum of internal capacitor voltages of Modules h is always a voltage which is equal to a DC bus voltage (V_DC) when the asymmetric modular multilevel converter (AMMC) is in a normal state.

4. The apparatus of claim 3, wherein:

an internal capacitor voltage of the Modules f configured with the full bridge is configured to be different in sequence by control; and

an internal capacitor voltage of a Module f 1 is ½

of the DC bus voltage, an internal capacitor voltage of a Module f 2 is ¼

of the DC bus voltage, and an internal capacitor voltage of a Module f N is 2<sup>−

N</sup> of the DC bus voltage.

5. The apparatus of claim 3, wherein:

when the arm is configured with only one Module h, two levels of +½ and

−

½

are implemented, and when the arm is configured with K Modules h, “

K+1”

levels in total are implemented from −

½

to +½

by the Modules h; and

a capacitor voltage reference value (V_DC) of the Module f is 1/K.

6. The apparatus of claim 3, wherein N Modules f and K Modules h implement a total of “

2^N·

K+1”

levels.

7. The apparatus of claim 3, wherein:

the Modules f remaining after excluding the Module h responsible for the maximum voltage have the full bridges; and

when there is one Module h, a sum of the capacitor voltages of N connected Modules f is V_DC(1−

2<sup>−

N</sup>) and a fault current is blocked by a capacitor voltage of 1/(1−

2<sup>−

N</sup>) times the capacitor voltage in a normal state when a problem occurs at a DC circuit.

8. The apparatus of claim 1, wherein, to apply the apparatus for controlling an asymmetric modular multilevel converter to an asymmetric cascaded H-bridge converter,

H-bridge converters are connected in series to configure the asymmetric cascaded H-bridge converter, and

the asymmetric cascaded H-bridge converter subdivides an output of a voltage source converter (Converter AC Out) of a single-level, a multi-level, and a multilevel converter (MMC) to output a new output (Modified AC Out) having over ten output voltage levels.

9. The apparatus of claim 8, wherein, when a level of the Converter AC Out is assumed to be a J level, a level of the Modified AC Out of the asymmetric cascaded H-bridge converter configured with N H-bridges is “

(J−

1)·

2^N+1.”

10. A method of controlling an asymmetric modular multilevel converter, comprising:

in control of an asymmetric arm configured with N Modules f configured with a full bridge and K Modules h configured with a half bridge between a V_DC positive input terminal (+) and a V_DC negative input terminal (−

),

each Module h is responsible for an equally divided voltage;

a sum of internal capacitor voltages of Modules h is always a voltage which is equal to a DC bus voltage (V_DC) when the AMMC is in a normal state; and

internal capacitor voltages of the Modules f configured with the full bridge are configured to be different in sequence by control.

11. The method of claim 10, wherein, when a current (i) flowing into an arm which configures a converter from a positive voltage portion of a converter DC voltage (V_DC) is considered, a correlation with a voltage V_C applied to a capacitor of module n is controlled on the basis of Expression 1 which is (V_DC/2ⁿ−

V_Cn)*i>

0.

12. The method of claim 11, wherein when (V_DC/2ⁿ−

V_Cn)>

0, a capacitor voltage of the module is equal to or lower than an optimal level and requires charging, and when i>

0, it is judged that a current flows through the arm in a direction from a high voltage to a low voltage of the DC bus and the module is controlled by a negative state (−

) to charge the capacitor.

13. The method of claim 11, wherein, when (V_DC/2ⁿ−

V_Cn)<

0, a capacitor voltage of a module is equal to or higher than an optimal level and requires discharging, and when i<

0, it is judged that a current flows through the arm in a direction from a negative voltage to a positive voltage of the DC bus and the module is controlled by a negative state (−

) to discharge the capacitor.

14. The method of claim 11, wherein:

among states not satisfying Expression 1, when values at the right and left sides of the expression are the same, the capacitor voltage is judged to be in an ideal state and the module is controlled by a zero state (0) to maintain the capacitor voltage without change or is controlled to repeat a positive state (+) or a negative state (−

); and

among the states not satisfying Expression 1, when the left side value of the expression is less than zero including two cases of (V_DC/2ⁿ−

V_Cn)<

0 while i >

0 and (V_DC/2ⁿ−

V_Cn)>

0 while i<

0, the module is controlled by a positive state (+) to discharge or charge the capacitor.

15. The method of claim 10, wherein an alternating current (AC) output voltage of the highest Module h which is responsible for the highest voltage is within a range of the V_DC which is the DC bus voltage and the capacitor voltage of the Module h is maintained at a level of 1/KV_DC.

16. The method of claim 10, wherein:

an upper asymmetric arm and a lower asymmetric arm are connected in series between a V_DC input terminal and a V_AC output terminal to configure the asymmetric modular multilevel converter;

modules of each arm are controlled so that a sum of the Module h voltages applied to each of the upper arm and the lower arm is V_DC; and

half of a total amount of the Modules h of the upper arm and the lower arm is always turned on or off.

17. The method of claim 16, wherein voltage control between Modules h is performed while comparing a voltage between modules so that a module having the lowest voltage is first charged and a module having the highest voltage is first discharged according to a flow of a current.