HALF BRIDGE DRIVER CIRCUITS

• US 20170163258A1
• Filed: 02/13/2017
• Published: 06/08/2017
• Est. Priority Date: 09/16/2014
• Status: Active Grant

• Current Assignee: Navitas Semiconductor Limited (Navitas Semiconductor Corp.)
• Original Assignee: Navitas Semiconductor, Inc.
• Inventors: Kinzer, Daniel Marvin, Sharma, Santosh, Zhang, Ju
• Granted Patent: US 9,960,764 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48257 connecting the wire to a die pad of the item
• CPC Class Codes: H01L 2224/49171 Fan-out arrangements
• CPC Class Codes: H02M 1/08 Circuits specially adapted for the generation of control voltages for semiconductor devices incorporated in static converters
• CPC Class Codes: H02M 1/36 Means for starting or stopping converters
• CPC Class Codes: H02M 1/38 Means for preventing simultaneous conduction of switches
• CPC Class Codes: H02M 3/1588 comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 19/017509 Interface arrangements
• CPC Class Codes: H03K 2217/0063 High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load
• CPC Class Codes: H03K 2217/0072 Low side switches, i.e. the lower potential [DC] or neutral wire [AC] being directly connected to the switch and not via the load
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

GaN-based half bridge power conversion circuits employ control, support and logic functions that are monolithically integrated on the same devices as the power transistors. In some embodiments, a low side GaN device communicates through one or more level shift circuits with a high side GaN device. Both the high side and the low side devices may have one or more integrated control, support and logic functions.

Claims

1. A half bridge GaN circuit, comprising:

a low side circuit, comprising;

a low side switch having a low side switch control gate and a first source,

a level shift driver, comprising;

a first level shift driver input connected to a first logic signal, wherein the first logic signal is referenced to the voltage of the first source, and

a level shift driver output, configured to transmit a first level shift input signal,

a low side switch driver, comprising;

a first low side switch driver input configured to receive a second logic signal, wherein the second logic signal is referenced to a voltage at the first source, and

a first low side switch driver output connected to the low side switch control gate and configured to transmit a low side switch control signal to the low side switch control gate, wherein the low side switch control signal is generated based on the second logic signal,

a first level shift circuit configured to receive the first level shift input signal and to generate a first level shift signal, and

a second level shift circuit configured to generate a second level shift signal; and

a high side circuit, comprising;

a high side switch having a high side switch control gate and a second source,

a first high side receiver circuit referenced to a voltage at the second source and configured to receive the first level shift signal and to generate a first high side driver control signal,

a second high side receiver circuit referenced to the voltage of the second source and configured to receive the second level shift signal and to generate a second high side driver control signal, and

a high side switch driver referenced to the voltage of the second source, wherein the high side switch driver comprises;

one or more logic inputs configured to receive the first and second high side driver control signals, and

a high side switch driver output connected to the high side switch control gate and configured to transmit a high side switch control signal to the high side switch control gate, wherein the high side switch control signal is generated base on the first and second high side driver control signals,

wherein the first and second high side receiver circuits are configured to prevent a change of voltage state of the high side control gate in response to voltage transients of the voltage of the second source.

2. The half bridge GaN circuit of claim 1, wherein the first level shift signal is configured to cause the high side switch to turn on and wherein the second level shift signal is configured to cause the high side switch to turn off.

3. The half bridge GaN circuit of claim 1, wherein:

the level shift driver further comprises;

an HS STP input configured to receive a high side shoot through protection signal from the low side switch driver, wherein the level shift driver is configured to generate the first level shift input signal based in part on the high side shoot through protection signal;

the low side switch driver further comprises;

an LS STP input configured to receive a low side shoot through protection signal from the level shift driver, wherein the low side switch driver is configured to generate the low side switch control signal based in part on the low side shoot through protection signal; and

the high side shoot through protection signal and the low side shoot through protection signal are respectively generated by the low side switch driver and the level shift driver so as to prevent the high side switch and the low side switch from being simultaneously on.

4. The half bridge GaN circuit of claim 3, wherein the level shift driver comprises a first pulse generator configured to generate a pulse in response to a high to low transition of the first logic signal and to transmit the pulse to the first level shift driver output as the low side shoot through protection signal.

5. The half bridge GaN circuit of claim 4, wherein the low side switch control gate is controlled according to a logical combination of the low side shoot through protection signal, the first logic signal, and the second logic signal.

6. The half bridge GaN circuit of claim 3, wherein the low side switch driver comprises a second pulse generator configured to generate a pulse in response to a high to low transition of the second logic signal and to transmit the pulse to the first level shift driver as the high side shoot through protection signal.

7. The half bridge GaN circuit of claim 6, wherein the high side switch control gate is controlled according to a logical combination of the high side shoot through protection signal, the first logic signal, and the second logic signal.

8. The half bridge GaN circuit of claim 3, wherein the first level shift circuit is configured to generate a pulse in response to a high to low transition of the first logic signal and to output the pulse as the first level shift signal, wherein, in response to the first level shift signal, the first high side receiver is configured to reduce a turn-off propagation delay of the high side control gate.

9. The half bridge GaN circuit of claim 1, wherein the high side circuit further comprises:

a first conductive element configured to pull up a voltage of the first level shift signal toward a voltage of a floating power supply;

a first pull up transistor configured to pull up the voltage of the first level shift signal toward the voltage of the floating power supply;

a second conductive element configured to pull up the voltage of the second level shift signal toward the voltage of the floating power supply; and

a second pull up transistor configured to pull up the voltage of the second level shift signal toward the voltage of the floating power supply.

10. A half bridge GaN circuit, comprising:

a low side circuit, comprising;

a low side switch having a low side switch control gate and a first source,

a level shift driver, comprising;

a first level shift driver input connected to a first logic signal, wherein the first logic signal is referenced to the voltage of the first source, and

a level shift driver output, configured to transmit a first level shift input signal,

a low side switch driver, comprising;

a first low side switch driver input configured to receive a second logic signal, wherein the second logic signal is referenced to a voltage at the first source, and

a first low side switch driver output connected to the low side switch control gate and configured to transmit a low side switch control signal to the low side switch control gate, wherein the low side switch control signal is generated based on the second logic signal,

a first level shift circuit configured to receive the first level shift input signal and to generate a first level shift signal, and

a second level shift circuit configured to generate a second level shift signal; and

a high side circuit, comprising;

a high side switch having a high side switch control gate and a second source,

a first high side receiver circuit referenced to a voltage at the second source and configured to receive the first level shift signal and to generate a first high side driver control signal,

a second high side receiver circuit referenced to the voltage of the second source and configured to receive the second level shift signal and to generate a second high side driver control signal, and

a high side switch driver referenced to the voltage of the second source, wherein the high side switch driver comprises;

one or more logic inputs configured to receive the first and second high side driver control signals, and

a high side switch driver output connected to the high side switch control gate and configured to transmit a high side switch control signal to the high side switch control gate, wherein the high side switch control signal is generated base on the first and second high side driver control signals,

wherein the first and second level shift signals comprise a plurality of pulses, and

wherein the high side switch gate control signal is generated in response to the pulses, and wherein durations of on and off times of the high side switch are based on durations of the pulses.

11. The half bridge GaN circuit of claim 10, wherein the first level shift signal is configured to cause the high side switch to turn on and wherein the second level shift signal is configured to cause the high side switch to turn off.

12. The half bridge GaN circuit of claim 10, wherein:

the level shift driver further comprises;

an HS STP input configured to receive a high side shoot through protection signal from the low side switch driver, wherein the level shift driver is configured to generate the first level shift input signal based in part on the high side shoot through protection signal;

the low side switch driver further comprises;

an LS STP input configured to receive a low side shoot through protection signal from the level shift driver, wherein the low side switch driver is configured to generate the low side switch control signal based in part on the low side shoot through protection signal; and

the high side shoot through protection signal and the low side shoot through protection signal are respectively generated by the low side switch driver and the level shift driver so as to prevent the high side switch and the low side switch from being simultaneously on.

13. The half bridge GaN circuit of claim 12, wherein the level shift driver comprises a first pulse generator configured to generate a first pulse in response to a high to low transition of the first logic signal and to transmit the first pulse to the first level shift driver output as the low side shoot through protection signal.

14. The half bridge GaN circuit of claim 13, wherein the low side switch control gate is controlled according to a logical combination of the low side shoot through protection signal, the first logic signal, and the second logic signal.

15. The half bridge GaN circuit of claim 12, wherein the low side switch driver comprises a second pulse generator configured to generate a first pulse in response to a high to low transition of the second logic signal and to transmit the first pulse to the first level shift driver as the high side shoot through protection signal.

16. The half bridge GaN circuit of claim 15, wherein the high side switch control gate is controlled according to a logical combination of the high side shoot through protection signal, the first logic signal, and the second logic signal.

17. The half bridge GaN circuit of claim 12, wherein the first level shift circuit is configured to generate a first pulse in response to a high to low transition of the first logic signal and to output the first pulse as the first level shift signal, wherein, in response to the first level shift signal, the first high side receiver is configured to reduce a turn-off propagation delay of the high side control gate.

18. The half bridge GaN circuit of claim 10, wherein the high side circuit further comprises:

a first conductive element configured to pull up a voltage of the first level shift signal toward a voltage of a floating power supply;

a first pull up transistor configured to pull up the voltage of the first level shift signal toward the voltage of the floating power supply;

a second conductive element configured to pull up the voltage of the second level shift signal toward the voltage of the floating power supply; and

a second pull up transistor configured to pull up the voltage of the second level shift signal toward the voltage of the floating power supply.

19. A half bridge GaN circuit, comprising:

a low side circuit, comprising;

a low side switch having a low side switch control gate and a first source,

a level shift driver, comprising;

a first level shift driver input connected to a first logic signal, wherein the first logic signal is referenced to the voltage of the first source, and

a level shift driver output, configured to transmit a first level shift input signal,

a low side switch driver, comprising;

a first low side switch driver input configured to receive a second logic signal, wherein the second logic signal is referenced to a voltage at the first source, and

a first low side switch driver output connected to the low side switch control gate and configured to transmit a low side switch control signal to the low side switch control gate, wherein the low side switch control signal is generated based on the second logic signal,

a first level shift circuit configured to receive the first level shift input signal and to generate a first level shift signal, and

a second level shift circuit configured to generate a second level shift signal; and

a high side circuit, comprising;

a high side switch having a high side switch control gate and a second source,

a first high side receiver circuit referenced to a voltage at the second source and configured to receive the first level shift signal and to generate a first high side driver control signal,

a second high side receiver circuit referenced to the voltage of the second source and configured to receive the second level shift signal and to generate a second high side driver control signal, and

a high side switch driver referenced to the voltage of the second source, wherein the high side switch driver comprises;

one or more logic inputs configured to receive the first and second high side driver control signals, and

a high side switch driver output connected to the high side switch control gate and configured to transmit a high side switch control signal to the high side switch control gate, wherein the high side switch control signal is generated base on the first and second high side driver control signals, and

a trigger circuit configured to, in response to a voltage of a first power supply referenced to the voltage of the second source being less than a threshold greater than the voltage of the second source, cause the high side switch to turn-off.

20. The half bridge GaN circuit of claim 19, wherein the first level shift signal is configured to cause the high side switch to turn on and wherein the second level shift signal is configured to cause the high side switch to turn off.

21. The half bridge GaN circuit of claim 19, wherein:

the level shift driver further comprises;

an HS STP input configured to receive a high side shoot through protection signal from the low side switch driver, wherein the level shift driver is configured to generate the first level shift input signal based in part on the high side shoot through protection signal;

the low side switch driver further comprises;

an LS STP input configured to receive a low side shoot through protection signal from the level shift driver, wherein the low side switch driver is configured to generate the low side switch control signal based in part on the low side shoot through protection signal; and

the high side shoot through protection signal and the low side shoot through protection signal are respectively generated by the low side switch driver and the level shift driver so as to prevent the high side switch and the low side switch from being simultaneously on.

22. The half bridge GaN circuit of claim 21, wherein the level shift driver comprises a first pulse generator configured to generate a pulse in response to a high to low transition of the first logic signal and to transmit the pulse to the first level shift driver output as the low side shoot through protection signal.

23. The half bridge GaN circuit of claim 22, wherein the low side switch control gate is controlled according to a logical combination of the low side shoot through protection signal, the first logic signal, and the second logic signal.

24. The half bridge GaN circuit of claim 21, wherein the low side switch driver comprises a second pulse generator configured to generate a pulse in response to a high to low transition of the second logic signal and to transmit the pulse to the first level shift driver as the high side shoot through protection signal.

25. The half bridge GaN circuit of claim 24, wherein the high side switch control gate is controlled according to a logical combination of the high side shoot through protection signal, the first logic signal, and the second logic signal.

26. The half bridge GaN circuit of claim 21, wherein the first level shift circuit is configured to generate a pulse in response to a high to low transition of the first logic signal and to output the pulse as the first level shift signal, wherein, in response to the first level shift signal, the first high side receiver is configured to reduce a turn-off propagation delay of the high side control gate.

27. The half bridge GaN circuit of claim 19, wherein the high side circuit further comprises:

a first conductive element configured to pull up a voltage of the first level shift signal toward a voltage of a floating power supply;

a first pull up transistor configured to pull up the voltage of the first level shift signal toward the voltage of the floating power supply;

a second conductive element configured to pull up the voltage of the second level shift signal toward the voltage of the floating power supply; and

a second pull up transistor configured to pull up the voltage of the second level shift signal toward the voltage of the floating power supply.