Method and System for DC-DC Voltage Converters

• US 20170168515A1
• Filed: 04/20/2016
• Published: 06/15/2017
• Est. Priority Date: 12/14/2015
• Status: Active Grant

• Current Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Original Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Inventors: Beck, David L.
• Granted Patent: US 9,785,166 B2
• Time in Patent Office: Days
• CPC Class Codes: G05F 1/575 characterised by the feedback circuit
• CPC Class Codes: H02M 1/0025 Arrangements for modifying reference values, feedback values or error values in the control loop of a converter
• CPC Class Codes: H02M 1/14 Arrangements for reducing ripples from dc input or output
• CPC Class Codes: H02M 1/15 using active elements
• CPC Class Codes: H02M 3/157 with digital control
• CPC Class Codes: H02M 3/158 including plural semiconductor devices as final control devices for a single load

Abstract

On embodiment pertains to a method including determining if an amplitude of an error signal has entered steady state. If the amplitude of the error signal has not entered steady state, then amplify with a high gain the amplitude of the AC component of the error signal. If the amplitude of the error signal has entered steady state, then initiate a timer. Determining if the amplitude of the error signal has remained in steady state while the timer runs. If the amplitude of the error signal has remained in steady state while the timer runs, then amplify with a low gain the amplitude of the AC component of the error signal.

Claims

1. An apparatus, comprising:

an error amplifier having a positive input coupled to a reference voltage, and a negative input coupled to an output voltage sense signal;

wherein an output of the error amplifier is coupled to an input of an AC path, an input of a DC path and an input of a gain reduction circuit;

the gain reduction circuit having an input coupled to an output of the AC path;

a beta gain circuit having an input coupled to an output of a summer;

the summer having inputs coupled to an output of the gain reduction circuit, an output of the DC path, and an output of the beta gain circuit; and

wherein the output of the summer is the sum of the signals at the inputs of the summer coupled to the outputs of the gain reduction circuit and the DC path, less the signal at the input of the summer coupled to the output of the beta gain circuit.

2. The apparatus of claim 1, wherein the gain reduction circuit comprises an alpha gain circuit coupled to a variable gain circuit.

3. The apparatus of claim 1 further comprising a PWM signal generator configured to receive the output of the summer, and having an output configured to provide a PWM signal.

4. The apparatus of claim 3, further comprising a power stage having an input coupled to the output of the PWM signal generator, and which provides the output voltage sense signal.

5. The apparatus of claim 1, wherein the DC path comprises an integrator.

6. The apparatus of claim 1, wherein the AC path comprises a band reject filter.

7. The apparatus of claim 6, wherein the band reject filter is a ripple filter.

8. The apparatus of claim 1 wherein the gain reduction circuit comprises:

an alpha gain circuit; and

a variable gain circuit coupled to the alpha gain circuit.

9. The apparatus of claim 8 wherein the variable gain circuit comprises:

a steady state range detector;

a timer circuit having an input coupled to an output of the steady state range detector;

an AND gate having inputs respectively coupled to the outputs of the steady state range detector and the timer circuit; and

an attenuator having inputs respectively coupled to the outputs of the AND gate and the alpha gain circuit.

10. The apparatus of claim 9, wherein the steady state range detector comprises:

an absolute value circuit;

a threshold reference circuit; and

a threshold detection circuit having inputs respectively coupled to the outputs of the absolute value circuit and the threshold reference circuit.

11. The apparatus of claim 1 further comprising:

a first delay circuit coupled to the output of the summer;

a subtractor having inputs coupled to an output of the DC path and an output of the delay circuit;

wherein the output of the subtractor is the signal at the output of the delay circuit less the signal at the output of the DC path;

a second summer having inputs coupled to the outputs of the subtractor and a second delay circuit;

wherein an output of the second summer is coupled to the input of the beta gain circuit; and

wherein the output of the beta gain circuit is coupled to the input of the second delay circuit.

12. A system comprising:

a control loop comprising;

an error amplifier having a positive input coupled to a reference voltage, and a negative input coupled to an output voltage sense signal;

wherein an output of the error amplifier is coupled to an input of an AC path, an input of a DC path and an input of a compensator;

the compensator comprising;

a gain reduction circuit having inputs coupled to an output of the AC path, and the output of the error amplifier;

a beta gain circuit having an input coupled to an output of a summer;

a summer having inputs coupled to an output of the gain reduction circuit, an output of the DC path, and an output of the beta gain circuit; and

wherein the output of the summer is the sum of the signals at the inputs of the summer coupled to the outputs of the gain reduction circuit and the DC path, less the signal at the input of the summer coupled to the output of the beta gain circuit;

a PWM signal generator configured to receive the output of the summer, and having an output configured to provide a PWM signal; and

a power stage having an input coupled to an output of the PWM signal generator, and configured to generate the output voltage sense signal.

13. The system of claim 12, further comprising a load coupled to an output of the power stage.

14. The system of claim 13, wherein the load comprises a processor and a memory.

15. The system of claim 12, wherein the gain reduction circuit comprises an alpha gain circuit coupled to a variable gain circuit.

16. The system of claim 12, wherein the DC path comprises an integrator.

17. The system of claim 12, wherein the AC path comprises a band reject filter.

18. The system of claim 17, wherein the band reject filter is a ripple filter.

19. A method, comprising:

determining if an amplitude of an error signal has entered steady state;

if the amplitude of the error signal has not entered steady state, then amplify with a high gain the amplitude of the AC component of the error signal;

if the amplitude of the error signal has entered steady state, then initiate a timer;

determining if the amplitude of the error signal has remained in steady state while the timer runs; and

if the amplitude of the error signal has remained in steady state while the timer runs, then amplify with a low gain the amplitude of the AC component of the error signal.

20. The method of claim 19, further comprising calculating an absolute value of an amplitude of an AC component of the error signal;

and

wherein determining if an error signal has entered steady state further comprises determining if the absolute value of the amplitude of the AC component of the error signal is within one or more steady state threshold levels.

21. The method of claim 20, further comprising generating a PWM signal.

22. The method of claim 19, further comprising:

determining if the amplitude of the error signal has exited steady state;

if the error signal has not exited steady state, then amplify with the low gain the amplitude of the AC component of the error signal; and

if the amplitude of the error signal has exited steady state, then amplify with the high gain the amplitude of the AC component of the error signal.

23. The method of claim 22, further comprising calculating an absolute value of the amplitude of an AC component of the error signal;

and

wherein determining if the amplitude of the error signal has exited steady state further comprises determining if the absolute value of the amplitude of the AC component of the error signal is outside of one or more steady state threshold levels.