SEMICONDUCTOR STRUCTURE WITH AIRGAP

• US 20170170056A1
• Filed: 02/21/2017
• Published: 06/15/2017
• Est. Priority Date: 09/08/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: JAFFE, Mark D., LIU, Qizhi, STAMPER, Anthony K., JOSEPH, Alvin J.
• Granted Patent: US 9,917,005 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02233 of the semiconductor substrate or a semiconductor layer
• CPC Class Codes: H01L 21/02238 silicon in uncombined form, i.e. pure silicon
• CPC Class Codes: H01L 21/02255 formation by thermal treatment H01L21/02252 takes precedence; after treatment of an insulating film H01L21/3105 and subgroups
• CPC Class Codes: H01L 21/0273 characterised by the treatment of photoresist layers
• CPC Class Codes: H01L 21/26533 of electrically inactive species in silicon to make buried insulating layers
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/76283 Lateral isolation by refilling of trenches with dielectric material
• CPC Class Codes: H01L 21/76286 Lateral isolation by refilling of trenches with polycristalline material
• CPC Class Codes: H01L 21/76289 Lateral isolation by air gap
• CPC Class Codes: H01L 21/764 Air gaps H01L21/76264 takes precedence
• CPC Class Codes: H01L 27/1207 combined with devices in contact with the semiconductor body, i.e. bulk/SOI hybrid circuits
• CPC Class Codes: H01L 29/0649 Dielectric regions, e.g. SiO2 regions, air gaps
• CPC Class Codes: H01L 29/0653 adjoining the input or output region of a field-effect device, e.g. the source or drain region
• CPC Class Codes: H01L 29/66651 with a single crystalline channel formed on the silicon substrate after insulating device isolation
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/66772 Monocristalline silicon transistors on insulating substrates, e.g. quartz substrates H01L29/66666 takes precedence; thin film FinFETs H01L29/66795
• CPC Class Codes: H01L 29/78 with field effect produced by an insulated gate H01L29/7725, H01L29/775, H01L29/778 take precedence
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78666 : with normal-type structure, e.g. with top gate

Abstract

A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.

Claims

1. A method, comprising:

forming a lateral undercut in a bulk substrate starting at a bottom of at least one deep trench structure; and

filling the at least one deep trench structure with material to form an airgap from the lateral undercut in the bulk substrate under the active region,

wherein the lateral undercut is formed by etching with XeF₂ and the material is formed directly on sidewall structures on sidewalls of the at least one deep trench structure.

2. The method of claim 1, further comprising completely filling of the at least one deep trench structure with the material to form the airgap from the lateral undercut in the bulk substrate under the active region.

3. The method of claim 2, wherein the sidewall structures comprise depositing oxide within the at least one deep trench structure and removing of the oxide from a bottom surface of the at least one deep trench structure to expose the bulk substrate for subsequent etching.

4. The method f claim 3, wherein the sidewall structures are formed prior to forming the lateral undercut in the bulk substrate.

5. The method of claim 3, further comprising removing residual material of the sidewall structures from a surface of a substrate material on the bulk substrate.

6. The method of claim 1, further comprising forming a transistor over the airgap.

7. The method of claim 6, wherein the transistor is formed as a completely isolated transistor.

8. The method of claim 1, wherein a location of the airgap is directly under a transistor channel.

9. The method of claim 8, wherein the airgap is in contact with the transistor channel.

10. The method of claim 1, wherein the material is polysilicon material deposited within the at least one deep trench structure.

11. The method of claim 1, wherein the sidewall structures are on vertical portions of the at least one deep trench structure.