VERTICAL FIELD-EFFECT-TRANSISTORS HAVING MULTIPLE THRESHOLD VOLTAGES

• US 20170170298A1
• Filed: 02/02/2017
• Published: 06/15/2017
• Est. Priority Date: 12/09/2015
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: BALAKRISHNAN, Karthik, HASHEMI, Pouya, REZNICEK, Alexander, CHENG, Kangguo
• Granted Patent: US 9,941,370 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/045 by their particular orientation of crystalline planes
• CPC Class Codes: H01L 29/0676 oriented perpendicular or at an angle to a substrate
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/775 with one dimensional charge carrier gas channel, e.g. quantum wire FET
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

Various embodiments disclose a method for fabricating a semiconductor structure including a plurality of vertical transistors each having different threshold voltages. In one embodiment the method includes forming a structure having at least a substrate, a source contact layer on the substrate, a first spacer layer on the source contact layer, a replacement gate on the first spacer layer, a second spacer layer on the replacement gate, and an insulating layer on the second spacer layer. A first trench is formed in a first region of the structure. A first channel layer having a first doping concentration is epitaxially grown in the first trench. A second trench is formed in a second region of the structure. A second channel layer having a second doping concentration is epitaxially grown in the second trench. The second doping concentration is different from the first doping concentration.

Claims

1. A method for fabricating a semiconductor structure comprising a plurality of vertical transistors each having different threshold voltages, the method comprising:

forming a structure comprising at least a substrate, a source contact layer on the substrate, a first spacer layer on the source contact layer, a replacement gate on the first spacer layer, a second spacer layer on the replacement gate, and an insulating layer on the second spacer layer;

forming a first trench in a first region of the structure, the first trench extending from a top surface of the insulating layer down to a top surface of the source contact layer;

epitaxially growing a first channel layer with a first doping concentration up from the top surface of the source contact layer, the first channel layer filling the first trench;

forming a second trench in a second region of the structure, the second trench extending from the top surface of the insulating layer down to the top surface of the source contact layer; and

epitaxially growing a second channel layer with a second doping concentration up from the top surface of the source contact layer, the second channel layer filling the second trench, where the second doping concentration is different from the first doping concentration.

2. The method of claim 1, further comprising:

forming a counter-doped layer in contact with the substrate.

3. The method of claim 1, further comprising:

after epitaxially growing the first channel material, forming a hardmask over the first region of the structure prior to forming the second trench.

4. The method of claim 1, further comprising:

prior to epitaxially growing the first channel layer, forming a protective layer on exposed portions of the replacement gate within the first trench; and

prior to epitaxially growing the second channel layer, forming a protective layer on exposed portions of the replacement gate within the second trench.

5. The method of claim 1, further comprising:

recessing the first and second channel layers, the recessing leaving a first portion of the first and second channel layers above the second spacer layer;

after the recessing, forming a first mask above and in contact with the first channel layer and forming a second mask above and in contact with second channel layer;

after forming the first and second masks, removing the insulating layer exposing the first portion of the first and second channel layers; and

performing a lateral etch of the first portion of the first and second channel layers, the lateral etch narrowing the first portion of the first and second channel layers and a second portion of the first and second channel layers below a top surface of the second spacer layer.

6. The method of claim 5, further comprising:

forming a first drain region and second drain region on the first and second portions of the first and second channel layers, respectively.

7. The method of claim 6, further comprising:

forming a third spacer layer on and in contact with sidewalls of the first mask and sidewalls of the first drain region, the third spacer layer also being formed on and in contact with a top surface of the second spacer layer in the first region of the structure; and

forming a fourth spacer layer on sidewalls of the second mask and sidewalls of the second drain region, the fourth spacer layer also being formed on and in contact with a top surface of the second spacer layer in the second region of the structure.

8. The method of claim 7, further comprising:

removing portions of the structure not underlying the third and fourth spacer layers down to the first spacer layer.

9. The method of claim 8, further comprising:

removing a portion of the replacement gate under the third spacer layer and a portion of the replacement gate under the fourth spacer layer, the removing exposing sidewalls of the first channel layer and the second channel layer.

10. The method of claim 9, further comprising:

forming a first metal gate structure on and in contact with the exposed sidewalls of the first channel layer, a portion of the first spacer layer under the third spacer layer, and a portion of the second spacer layer under the third spacer layer; and

forming a second metal gate structure on and in contact with the exposed sidewalls of the second channel layer, a portion of the first spacer layer under the fourth spacer layer, and a portion of the second spacer layer under the fourth spacer layer.

11. The method of claim 10, wherein forming each of the first and second metal gate structure comprises:

forming a first dielectric layer on and in contact with the exposed sidewalls of the first channel layer, the portion of the first spacer layer under the third spacer layer, and the portion of the second spacer layer under the third spacer layer; and

forming a second dielectric layer on and in contact with the exposed sidewalls of the second channel layer, the portion of the first spacer layer under the fourth spacer layer, and the portion of the second spacer layer under the fourth spacer layer.

12. The method of claim 11, wherein forming each of the first and second metal gate structure further comprises:

forming a first metal layer in contact with and conforming to the first dielectric layer; and

forming a second metal layer in contact with and conforming to the second dielectric layer.

13. The method of claim 10, further comprising:

forming recessed metal gate fill layers on each side of the first and second metal gate structures.

14. The method of claim 13, wherein forming the recessed metal gate fill layers comprises:

depositing a gate fill material over and in contact with the first and second regions of the structure; and

removing a portion of the metal gate fill layers down to a top surface of the second spacer layer.

15. The method of claim 14, further comprising:

patterning the recessed metal gate fill layers, wherein the patterning at least exposes a top surface of the first spacer layer between the first and second metal gate structures.

16. The method of claim 14, further comprising:

after the portion of the metal gate fill layers has been removed, removing a portion of the first metal gate structure and a portion of the second metal gate structure down to the top surface of the second spacer layer.

17. The method of claim 13, further comprising:

depositing a dielectric layer over the first and second regions of the structure;

forming a first contact trench through the dielectric layer exposing at least a top surface of the recessed metal gate fill layer on at least a first side of the first metal gate structure; and

forming a second contact trench through the dielectric layer exposing at least a top surface of the recessed metal gate fill layer on at least a first side of the second metal gate structure.

18. The method of claim 17, further comprising:

forming a contact in the first contract trench; and

forming a contact in the second contact trench.

19. The method of claim of claim 13, further comprising:

after the recessed metal gate fill layers have been formed, depositing a dielectric layer over the first and second regions of the structure;

forming a first contact trench through the dielectric layer exposing a portion of the first drain region and a region of the first portion of the first channel layer; and

forming a second contact trench through the dielectric layer exposing a portion of the second drain region and a region of the first portion of the second channel layer.

20. The method of claim of claim 19, further comprising:

forming a contact in the first contract trench; and

forming a contact in the second contact trench.