SEMICONDUCTOR DEVICE AND ELECTRIC POWER CONTROL APPARATUS

• US 20170170819A1
• Filed: 02/28/2017
• Published: 06/15/2017
• Est. Priority Date: 07/15/2015
• Status: Active Grant

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Renesas Electronics Corporation
• Inventors: KANDA, Ryo, MAEDA, Masatoshi, KUROIWA, Hiroshi, YAMAZAKI, Koichi, TODA, Tetsu
• Granted Patent: US 10,224,921 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/761 PN junctions
• CPC Class Codes: H01L 2224/05554 being square
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48096 the kinked part being in proximity to the bonding area on the semiconductor or solid-state body
• CPC Class Codes: H01L 2224/48139 with an intermediate bond, e.g. continuous wire daisy chain
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4903 Connectors having different sizes, e.g. different diameters
• CPC Class Codes: H01L 23/528 Geometry or layout of the interconnection structure H01L27/0207 takes precedence; algorithms G06F30/00
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0642 Isolation within the component, i.e. internal isolation
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/404 Multiple field plate structures
• CPC Class Codes: H01L 29/42368 : the thickness being non-uniform
• CPC Class Codes: H01L 29/7823 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7835 : with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
• CPC Class Codes: H01L 29/7838 : without inversion channel, e.g. buried channel lateral MISFETs, normally-on lateral MISFETs, depletion-mode lateral MISFETs
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/13055 : Insulated gate bipolar transistor [IGBT]
• CPC Class Codes: H01L 2924/13091 : Metal-Oxide-Semiconductor Field-Effect Transistor [MOSFET]
• CPC Class Codes: H03K 17/0822 : in field-effect transistor switches
• CPC Class Codes: H03K 17/567 : Circuits characterised by the use of more than one type of semiconductor device, e.g. BIMOS, composite devices such as IGBT
• CPC Class Codes: H03K 2217/0081 : Power supply means, e.g. to the switch driver
• CPC Class Codes: H03K 3/356 : Bistable circuits
• CPC Class Codes: H03K 3/356113 : using additional transistors in the input circuit
• CPC Class Codes: H03K 5/01 : Shaping pulses discrimination against noise or interference H03K5/125
• CPC Class Codes: H03K 5/04 : by increasing duration; by decreasing duration
• CPC Class Codes: H03K 5/24 : the characteristic being amplitude
• CPC Class Codes: H03K 5/2472 : using field effect transistors H03K5/2436 takes precedence
• CPC Class Codes: H03K 5/2481 : with at least one differential stage

Abstract

A driver IC includes a ring-shaped termination area, and a first area and a second area that are respectively arranged outside and inside the termination area on a layout. A sense MOS that is arranged between a floating terminal and a first sense node and is driven at a power supply voltage is formed in the termination area. A fault detection circuit that detects presence of a fault when a voltage of the first sense node is higher than a decision voltage that has been determined in advance in a period of time that a low side driver is driving a low side transistor into an ON state is formed in the first area.

Claims

1. A semiconductor device comprising:

a floating terminal configured to be coupled to a floating voltage source;

a first circuit including a low side driver, the first circuit being configured to operate based on a first power supply voltage and a reference voltage;

a second circuit including a high side driver, the second circuit being configured to operate based on a second power supply voltage and the floating voltage;

a first sense MOS transistor coupled between the floating terminal and a first sense node, a gate of the first sense MOS transistor being configured to receive the first power supply voltage; and

a fault detection circuit configured to detect that a voltage of the first sense node exceeds a first decision voltage when the low side driver is activated.

2. The semiconductor device according to claim 1,

wherein the first sense MOS transistor is depletion type.

3. The semiconductor device according to claim 1,

wherein the fault detection circuit includes:

a filter circuit configured to smooth the voltage of the first sense node; and

a first comparator circuit configured to compare an output voltage of the filter circuit with the first decision voltage.

4. The semiconductor device according to claim 1,

wherein the fault detection circuit further configured to detect that the voltage of the first sense node falls below a second decision voltage when the low side driver is inactivated and the high side driver is activated.