SELF-CHARACTERIZING HIGH-SPEED COMMUNICATION INTERFACES

• US 20170176534A1
• Filed: 12/18/2015
• Published: 06/22/2017
• Est. Priority Date: 12/18/2015
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ranganathan, Sridharan, Chellappan, Satheesh
• Application Number:
  US14/975,691
• Publication Number:
  US 20170176534A1
• Time in Patent Office: Days
• CPC Class Codes: G01R 31/31716 Testing of input or output with loop-back
• CPC Class Codes: G01R 31/31723 Hardware for routing the test signal within the device under test to the circuits to be tested, e.g. multiplexer for multiple core testing, accessing internal nodes routing the test signal to or from the device under test G01R31/31926
• CPC Class Codes: G01R 31/31724 Test controller, e.g. BIST state machine for scan test G01R31/318555
• CPC Class Codes: G01R 31/3177 Testing of logic operation, e.g. by logic analysers
• CPC Class Codes: G01R 31/3187 Built-in tests

Abstract

Logic controlling a local link interface enables in-band self-testing of the local link interface, the connected link interface of a remote device, and the link connecting the two. Logic configures a loopback in the remote device using an in-band protocol such as MIPI. The loopback may include all the link lanes or only a selected subset. The logic then isolates the local physical layer from upstream components and causes one or more test patterns to be sent through the local link interface and through the link to the loopback. The signals returning to the local link interface from the loopback are collected and compared with the original test patterns by an on-board checker in the link interface. The results, or a metric such as BER derived from the results, can then be accessed without requiring a custom dedicated test port.

Claims

1. A system-on-chip, comprising:

a physical layer;

a physical-layer adapter coupled to the physical layer;

logic coupled to the physical-layer adapter wherein the logic is to initiate a self-test on a link interface between the system-on-chip and a remote device; and

a pattern generator coupled to a transmit lane of the physical layer, the pattern generator to generate test-pattern-generating instructions associated with the self-test.

2. The system-on-chip of claim 1 further comprising an isolator that prevents the physical layer from sending signals to a receiver controller or receiving signals from a transmitter controller.

3. The system-on-chip of claim 1 further comprising a fabric-coupled register storing at least one of the test-pattern-generating instructions or test results.

4. The system-on-chip of claim 1 further comprising a pattern checker coupled to a receive lane of the physical layer, the pattern checker to receive test results from the remote device.

5. The system-on-chip of claim 1 further comprising a multiplexer combining a transmitter controller output and an output of the pattern generator into a transmit path of the physical layer.

6. The system-on-chip of claim 5, wherein the pattern generator and the pattern checker are combined within a single module.

7. A system, comprising:

a host physical layer associated with a host device;

a remote physical layer associated with a remote device;

an interface to link the host physical layer and the remote physical layer,

wherein the remote device comprises a loopback to direct a signal transmitted from the host device back to the remote device, and

wherein the loopback is configurable by the host physical layer.

8. The system of claim 7 further comprising an isolator between the host physical layer and a communication controller on the host device,

wherein the isolator is configurable by the host physical layer.

9. The system of claim 7, wherein the loopback is configured in a physical-layer adaptor on the remote device.

10. The system of claim 7 further comprising a transmit pad and a receive pad within the interface wherein a subset of an available set of lanes in the transmit pad are configured into the loopback.

11. A non-transitory machine-readable storage medium containing instructions that, when executed, cause a machine to:

trigger a link interface to generate a control signal in an in-band protocol;

configure a remote device to a loopback mode using the in-band protocol through one or more lanes of a communication link;

send a test pattern to a remote device; and

receive a returning pattern from the remote device.

12. The non-transitory machine-readable storage medium of claim 11 containing instructions that, when executed, cause the machine to calculate an operating margin of the link interface based on the returning pattern and the test pattern.

13. The non-transitory machine-readable storage medium of claim 11, wherein the in-band protocol is Mobile Industry Processing Interface.

14. The non-transitory machine-readable storage medium of claim 11, wherein to trigger the link interface to generate a control signal in the in-band protocol comprises a reset of the link interface.

15. The non-transitory machine-readable storage medium of claim 11, wherein to configure the remote device in the loopback mode using the in-band protocol comprises configuring the remote device during operation of the link interface in a first mode;

wherein to send the test pattern to the remote device and to receive a returning pattern from the remote device comprise transmission of the test pattern and collection of the returning pattern during operation of the link interface in a second mode; and

wherein the first mode differs from the second mode.

16. The non-transitory machine-readable storage medium of claim 15, wherein the first mode is a low-speed mode and the second mode is a high-speed mode.

17. The non-transitory machine-readable storage medium of claim 15, wherein the first mode comprises pulse-width modulation.

18. The non-transitory machine-readable storage medium of claim 11, wherein the test pattern comprises at least one of a Compliant Random Pattern and a Compliant Jitter Tolerance Pattern.

19. The non-transitory machine-readable storage medium of claim 12 containing instructions that, when executed, cause the machine to further output the calculated operating margin.

20. The non-transitory machine-readable storage medium of claim 12, wherein the operating margin includes a bit error rate.