SYSTEMS, METHODS AND DEVICES FOR STANDBY POWER SAVINGS

• US 20170177068A1
• Filed: 12/17/2015
• Published: 06/22/2017
• Est. Priority Date: 12/17/2015
• Status: Abandoned Application

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Cooper, Barnes, Rathnakar, Vidoot Ponnala
• Application Number:
  US14/972,461
• Publication Number:
  US 20170177068A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/263 Arrangements for using multiple switchable power supplies, e.g. battery and AC G06F1/30 takes precedence
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A power delivery system of a computing system can switch the computing platform from a set of main rails to a standby rail in a low-power state. For example, using a power optimizer framework, a platform controller hardware (PCH) and/or platform management controller (PCU) can transition an idle computing system to a low-power state using a standby rail with the main rails off. The PCU can instruct a processor in a C10 state to switch from main power rails to a standby rail. Once confirmed that the processor is in the C10 state, the PCU can turn off a processor voltage regulator and assert a platform sleep signal. After confirming the platform has entered the sleep state in which the platform has moved to the standby rails, the PCH or PCU can request a power supply to turn off the main rails but leave the standby rail active.

Claims

1. A system for transitioning to a low-power state, comprising:

a power supply electrically coupled to the system, the power supply comprising;

a main power output; and

a standby power output;

a processor receiving power from the main power output and the standby power output;

a south power management unit (PMC) coupled to the power supply and south side platform components; and

a north power management control unit (PCU) coupled to the power supply and the processor, the PCU configured to;

determine that the system is in an idle state;

transmit north side idle constraints to the PMC;

receive south side idle constraints from the PMC;

transition the processor to the low-power state, the low-power state causing the processor to transition from a main power rail to a standby power rail;

transmit a system transition signal to cause system components to switch from the main power output to the standby power output;

determine that the north side idle constraints and south side idle constraints have been met; and

transmit a request to turn off the power supply, the request causing the power supply to turn off the main power rail and leave the standby power rail active.

2. The system of claim 1, wherein the power supply is an advanced technology extended (ATX) multi-rail power supply.

3. The system of claim 1, wherein the power supply is an advanced technology extended (ATX) single-rail power supply.

4. The system of any of claim 1, wherein the low-power state of the processor is a C10 package state.

5. The system of any of claim 1, wherein the system transition signal is a SLEEP S ZERO (SLP_S0#) signal.

6. The system of any of claim 1, wherein the PCU is further configured to receive a signal indicating the processor has entered the low-power state, the low-power state causing the processor to transition from the main power rail to the standby power rail.

7. The system of any of claim 1, wherein the processor is configured to request a processor voltage regulator transition to an off state, when the processor transitions to the low-power state.

8. The system of claim 7, wherein processor voltage regulator is a fully integrated voltage regulator (FIVR).

9. A power control unit (PCU) device for reducing power consumption, comprising:

a power supply interface configured to send a sleep signal and an on/off signal to a power supply;

a central processing unit (CPU) interface configured to communicate a power state of a CPU;

a system interface configured to communicate to computing system components a low-power state switch from a main power rail to a standby power rail; and

a processor configured to;

determine that hardware threads of the CPU are idle;

receive platform idle constraints;

cause the processor to enter a low-power state, the low-power state causing the processor to transition from the main power rail to the standby power rail;

transmit a system transition signal to cause the computing system components to switch from the main power rail to the standby power rail; and

when the platform idle constraints are met, transmit a request to turn off the power supply, the request causing the power supply to turn off the main power rail and leave the standby rail active.

10. The device of claim 9, wherein the processor is further configured to wait a settling time between transmitting the instruction causing the processor to enter the low-power state and transmitting the system transition signal.

11. The device of claim 9, wherein the power state is a package C-State.

12. The device of claim 9, wherein the power state is a C10 state.

13. The device of any of claim 9, wherein the processor is further configured to determine a settling time for the computing system components when transitioning from the main rail to the standby rail based at least in part on a power framework that describes a maximum settling time of the computing system components.

14. A method of transitioning to a low-power state in a computing platform, comprising:

determining that a computing system is in an idle state;

receiving platform idle constraints;

causing a processor to enter the low-power state, the low-power state causing the processor to transition from a main power rail to a standby power rail;

receiving a signal indicating the processor has entered the low-power state;

requesting a processor voltage regulator to transition to an off state;

asserting a platform sleep signal;

determining the platform idle constraints have been met; and

transmitting a request to turn off a power supply, the request causing the power supply to turn off the main power rail but leave the standby rail active.

15. The method of claim 14, further comprising waiting a settling time between asserting the platform sleep signal and transmitting the request to turn off the power supply.

16. The method of claim 15, wherein the settling time is 100 milliseconds.

17. The method of claim 14, further comprising determining that components of the computing platform are in an idle state after asserting the platform sleep signal.

18. The method of claim 17, wherein asserting the platform sleep signal further comprises asserting a SLEEP S ZERO (SLP_S0#) signal.

19. The method of claim 14, wherein turning off the power supply further comprises de-asserting a power supply on (PS_ON#) signal.

20. A method of transitioning from a low-power state in a computing platform, comprising:

determining that a wake-up event has occurred;

transmitting a request to turn on a power supply, the request causing the power supply to turn on a main power rail;

transmitting a system transition signal to cause system components to switch from a standby power rail to the a main power rail; and

transmitting an instruction causing a central processing unit (CPU) to transition from the low-power state to an active state, the transition causing the CPU to transition from the standby power rail to the main power rail.

21. The method of claim 20, wherein transmitting a system transition signal further comprises deasserting a SLEEP S ZERO (SLP_S0#) signal.

22. The method of claim 20, wherein transmitting a request to turn on a power supply further comprises asserting a power supply on (PS_ON#) signal.