USE OF A BIPHASE CODE MATCHED FILTER TO RECEIVE PROTOCOLS WITH CODE VIOLATIONS

• US 20170178435A1
• Filed: 12/17/2015
• Published: 06/22/2017
• Est. Priority Date: 12/17/2015
• Status: Active Grant

• Current Assignee: NXP B.V. (NXP Semiconductors NV)
• Original Assignee: NXP B.V. (NXP Semiconductors NV)
• Inventors: POSCH, Martin
• Granted Patent: US 9,786,109 B2
• Time in Patent Office: Days
• CPC Class Codes: G07C 2009/00365 in combination with a wake-up circuit
• CPC Class Codes: G07C 2009/00373 whereby the wake-up circuit is situated in the lock
• CPC Class Codes: G07C 2009/00793 by Hertzian waves
• CPC Class Codes: G07C 2209/61 Signal comprising different frequencies, e.g. frequency hopping
• CPC Class Codes: G07C 9/00309 operated with bidirectional data transmission between data carrier and locks
• CPC Class Codes: H04L 25/49 using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems spectral shaping H04L25/03828

Abstract

In accordance with various example embodiments, a method of receiving a protocol in the receiver, wherein the legacy protocol includes non-biphase encoded information, decoding the legacy protocol using a biphase decoder to produce a detected code, and correlating the detected code with a known code to verify the non-biphase encoded information.

Claims

1. A method of decreasing false detection of wake-up patterns of a receiver, comprising:

receiving a protocol in the receiver, wherein the protocol includes non-biphase encoded information having a plurality of bit lengths;

decoding the protocol using a biphase decoder to produce a detected code; and

correlating the detected code with a known code to verify the non-biphase encoded information.

2. The method of claim 1, wherein decoding the protocol further comprises decoding a code violation and wake up pattern respectively.

3. The method of claim 2, wherein decoding the code violation results in an irregular pattern of ones and zeroes.

4. The method of claim 1, wherein decoding the protocol further comprises using a Manchester matched filter to decode the protocol.

5. The method of claim 1, comprising over-sampling the detected code to produce a plurality of bits and inputting the plurality of bits into a correlator.

6. The method of claim 1, comprising decoding the wake up pattern to result in a regular pattern of ones and zeroes and adding the decoded code violation to the decoded wake up pattern to produce a sum pattern.

7. The method of claim 6, comprising over-sampling the sum pattern to produce a plurality of bits and inputting the plurality of bits into a correlator.

8. The method of claim 7, comprising correlating the sum pattern to a known pattern to decrease the false wake up rate of the receiver.

9. The method of claim 1, wherein the biphase decoder integrates the protocol over complete bit lengths to produce the detected code.

10. A receiver to decrease false wake-up patterns of a receiver circuit, comprising:

a receiver front end configured to receive a protocol, wherein the protocol includes non-biphase encoded information having a plurality of bit lengths;

a biphase decoder configured to decode the protocol to produce a detected code; and

a correlator configured to correlate the detected code with a known code to verify the non-biphase encoded information.

11. The receiver of claim 10, wherein the protocol includes a code violation and wake up pattern respectively.

12. The receiver of claim 11, wherein the code violation is decoded to result in an irregular pattern of ones and zeroes.

13. The receiver of claim 10, wherein the biphase decoder includes a Manchester matched filter to decode the protocol.

14. The receiver of claim 10, wherein the detected code is over-sampled to produce a plurality of bits and the plurality of bits is input into a correlator.

15. The receiver of claim 10, wherein the wake up pattern is decoded to result in a regular pattern of ones and zeroes and the decoded code violation is added to the decoded wake up pattern to produce a sum pattern.

16. The receiver of claim 15, wherein the sum pattern is over-sampled to produce a plurality of bits and the plurality of bits is input into a correlator.

17. The receiver of claim 16, wherein the sum pattern is correlated to a known pattern to decrease the false wake up rate of the receiver.

18. The receiver of claim 10, wherein the biphase decoder integrates the protocol over complete bit lengths to produce the detected code.