METHOD FOR INTERCONNECTING STACKED SEMICONDUCTOR DEVICES

• US 20170179082A1
• Filed: 01/09/2017
• Published: 06/22/2017
• Est. Priority Date: 09/27/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Zhao, Junfeng
• Granted Patent: US 9,899,354 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/50 Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
• CPC Class Codes: H01L 21/565 Moulds
• CPC Class Codes: H01L 2224/12105 Bump connectors formed on an encapsulation of the semiconductor or solid-state body, e.g. bumps on chip-scale packages
• CPC Class Codes: H01L 2224/32145 the bodies being stacked
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73217 Layer and HDI connectors
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/73267 Layer and HDI connectors
• CPC Class Codes: H01L 2224/8203 Reshaping, e.g. forming vias
• CPC Class Codes: H01L 2224/82039 using a laser
• CPC Class Codes: H01L 2224/82047 by mechanical means, e.g. severing, pressing, stamping
• CPC Class Codes: H01L 2224/92144 the second connecting process involving a build-up interconnect
• CPC Class Codes: H01L 2225/06506 Wire or wire-like electrical connections between devices
• CPC Class Codes: H01L 2225/0651 Wire or wire-like electrical connections from device to substrate
• CPC Class Codes: H01L 2225/06544 Design considerations for via connections, e.g. geometry or layout
• CPC Class Codes: H01L 2225/06548 : Conductive via connections through the substrate, container, or encapsulation
• CPC Class Codes: H01L 2225/06562 : at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 23/49816 : Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 24/19 : Manufacturing methods of high density interconnect preforms
• CPC Class Codes: H01L 24/96 : the devices being encapsulated in a common layer, e.g. neo-wafer or pseudo-wafer, said common layer being separable into individual assemblies after connecting
• CPC Class Codes: H01L 25/00 : Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereofdevices consisting of a plurality of solid state components formed in or on a common substrate H01L27/00; photovoltaic modules or arrays of photovoltaic cells H01L31/042 ; panels or arrays of photo electrochemical cells H01G9/2068
• CPC Class Codes: H01L 25/0657 : Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 : Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/12042 : LASER
• CPC Class Codes: H01L 2924/15311 : being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A method for making a semiconductor device includes forming rims on first and second dice. The rims extend laterally away from the first and second dice. The second die is stacked over the first die, and one or more vias are drilled through the rims after stacking. The semiconductor device includes redistribution layers extending over at least one of the respective first and second dice and the corresponding rims. The one or more vias extend through the corresponding rims, and the one or more vias are in communication with the first and second dice through the rims.

Claims

1-22. -22. (canceled)

23. A semiconductor assembly comprising:

a first die assembly including;

a first die having a first die upper surface and a first die lower surface, and

a first rim extending laterally from the first die, wherein the first rim includes a first upper rim face proximate the first die up er surface and a first lower rim face proximate the first die lower surface, the first die lower surface and the first lower rim face proximate input and output arrays for the semiconductor assembly;

a second die assembly over the first die assembly, the second die assembly including;

a second die, having a second die u er surface and a second die lower surface,

a second rim extending laterally away from the second die, wherein the second rim includes a second upper rim face proximate the second die upper surface and a second lower rim face proximate the second die lower surface, and

a plurality of conductive traces extending outwardly beyond the second die toward the second lower rim face;

wherein at least the first upper rim face is an upper most surface of the first die assembly and the second lower rim face is a bottom most surface of the second die assembly, and the plurality of conductive traces are interposed between the first upper rim face and the second lower rim face;

and

one or more vias extending through at least one of the first and second rims, the one or more vias in communication with the first and second dice through the plurality of conductive traces and at least one of the first or second rims.

24. The semiconductor assembly of claim 23, wherein the first and second rims are molded resin molded around the respective first and second dice.

25. The semiconductor assembly of claim 23 comprising dielectric portions formed over each of the first and second dice, the dielectric portions including the one or more rims, and the one or more vias extend through the dielectric portions.

26. The semiconductor assembly of claim 23, wherein the one or more vias are laterally spaced from the first and second dice.

29. The semiconductor assembly of claim 23, wherein the vias are drilled vias formed in at least one of the respective rims after stacking of the second die over the first die.

30. The semiconductor assembly of claim 23 comprising a plurality of dice including the first and second dice, rims extend laterally from each of the plurality of dice, the plurality of dice are in a stacked configuration, and the one or more vias extend through at least two of the respective rims of the plurality of dice.

31. The semiconductor assembly of claim 23, wherein the second die is staggered relative to the first die, the second die includes at least one exposed bond pad according to the staggering.

32. The semiconductor assembly of claim 31, wherein the one or more vias extend through the rim of the first die to the at least one exposed bond pad of the second die.

33. The semiconductor assembly of claim 23, wherein the first die assembly includes another plurality of conductive traces extending outwardly beyond the first die and toward the first rim.

34. The semiconductor assembly of claim 23, wherein the second lower rim face and the second die lower surface of the second die are flush.

35. The semiconductor assembly of claim 23, wherein the second upper rim face is above the second die upper surface of the second die.

36. The semiconductor assembly of claim 24, wherein the molded resin extends over one or more of the first or second dice.

37. The semiconductor assembly of claim 23, wherein at least a first portion of the plurality of conductive traces underlies the second die, and a second portion of the plurality of conductive traces underlies the second rim.

27. (canceled)

28. The semiconductor assembly of claim, the plurality of conductive traces provide a fan-out configuration of conductive traces extending beyond a footprint of the second die.

38. A method for making a semiconductor assembly comprising:

forming a first die assembly including;

forming a first rim on a first die, the first rim extending laterally from the first die, and the first rim includes an exposed upper rim face proximate a first die upper surface of the first die;

forming a second die assembly including;

forming a second rim on a second die, the second rim extending laterally from the second die, and the second rim includes an exposed lower rim face proximate a second die lower surface of the second die, and

forming a plurality of conductive traces extending beyond the second die to the exposed lower rim face;

layering the exposed lower rim face of the second die assembly over the exposed upper rim face of the first die assembly, the plurality of conductive traces interposed between the exposed upper rim face and the exposed lower rim face; and

forming one or more vias extending through at least one of the first and second rims, the one or more vias in communication with the first and second dice.

39. The method of claim 38, wherein forming first and second rims includes molding a dielectric portion over the first die and the second die, the first and second rims formed with the dielectric portion.

40. The method of claim 38 comprising:

forming a first reconstituted dice panel including a first plurality of dice molded in a panel frame, the first plurality of dice include the first die, and

forming a second reconstituted dice panel including a second plurality of dice molded in another panel frame, the second plurality of dice including the second die; and

forming the first and second rims includes surrounding a periphery of the dice in the first and second reconstituted dice panels with a dielectric material.

41. The method of claim 40 comprising sorting the dice in the first plurality of dice and second plurality of dice to ensure only operational dice are used to form the first and second reconstituted dice panels.

42. The method of claim 40 comprising separating individual assemblies of first and second dice from the first and second reconstituted dice panels.

43. The method of claim 38, wherein forming the one or more vias consists of one or more of laser drilling, mechanical drilling or chemical etching.

44. The method of claim 38, wherein forming the one or more vias includes forming one or more continuous vias through each of the first and second rims.

45. The method of claim 38 comprising forming another plurality of conductive traces extending beyond the first die to the first rim, the one or more vias in communication with the plurality of conductive traces of each of the first and second die assemblies.

46. The method of claim 38, wherein layering the exposed lower rim face of the second die assembly over the exposed upper rim face of the second die assembly includes staggering the second die relative to the first die to expose at least one bond pad of the second die.