SEMICONDUCTOR DEVICE

• US 20170179150A1
• Filed: 09/12/2016
• Published: 06/22/2017
• Est. Priority Date: 12/16/2015
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: SHIMURA, Yasuhiro
• Granted Patent: US 10,032,790 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 23/3736 Metallic materials H01L23/3732, H01L23/3733, H01L23/3735, H01L23/3737, H01L23/3738 take precedence
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 23/5283 Cross-sectional geometry
• CPC Class Codes: H10B 43/10 characterised by the top-view layout
• CPC Class Codes: H10B 43/27 the channels comprising vertical portions, e.g. U-shaped channels
• CPC Class Codes: H10B 43/35 with cell select transistors, e.g. NAND
• CPC Class Codes: H10B 43/50 characterised by the boundary region between the core and peripheral circuit regions

Abstract

According to one embodiment, a semiconductor device includes a substrate; a stacked body; a columnar portion; and a plate portion. The stacked body includes a plurality of electrode layers stacked with an insulator interposed. The electrode layers include first to third electrode layers. The first electrode layer is most proximal to the substrate. The second electrode layer is most distal to the substrate. The columnar portion and the plate portion are provided inside the stacked body. The plate portion extends along the stacking direction of the stacked body and along a first direction orthogonal to the stacking direction. The plate portion includes first to third portions. The third portion is provided between the first portion and the second portion. Widths of the first portion and the second portion along a second direction are narrower than a width of the third portion along the second direction.

Claims

1. A semiconductor device, comprising:

a substrate having a major surface;

a stacked body provided on the major surface of the substrate, the stacked body including a plurality of electrode layers stacked with an insulator interposed, the plurality of electrode layers including a first electrode layer, a second electrode layer, and a third electrode layer, the first electrode layer being most proximal to the major surface of the substrate, the second electrode layer being most distal to the major surface of the substrate, the third electrode layer being provided between the first electrode layer and the second electrode layer;

a columnar portion provided inside the stacked body, the columnar portion extending along a stacking direction of the stacked body, the columnar portion including a semiconductor body and a memory film, the memory film being provided between the semiconductor body and the electrode layers, the memory film including a charge storage portion inside the film; and

a plate portion provided inside the stacked body, the plate portion extending along the stacking direction of the stacked body and along a first direction orthogonal to the stacking direction, the plate portion including a plate conductor and a sidewall insulating film, the sidewall insulating film being provided between the plate conductor and the stacked body, the plate portion including a first portion, a second portion, and a third portion along the stacking direction of the stacked body, the third portion being provided between the first portion and the second portion,

a width of the first portion along a second direction being narrower than a width of the third portion along the second direction, the second direction being orthogonal to the first direction along the major surface of the substrate,

a width of the second portion along the second direction being narrower than the width of the third portion along the second direction.

2. The semiconductor device according to claim 1, wherein

the first portion is adjacent to a lower layer portion of the stacked body including the first electrode layer,

the second portion is adjacent to an upper layer portion of the stacked body including the second electrode layer, and

the third portion is adjacent to a middle portion of the stacked body including the third electrode layer.

3. The semiconductor device according to claim 1, wherein

the width of the plate portion along the second direction

becomes wider continuously along the stacking direction of the stacked body from the major surface of the substrate toward the third portion, and

becomes narrower continuously along the stacking direction of the stacked body from the third portion toward an upper surface of the stacked body.

4. The semiconductor device according to claim 1, wherein

the plate conductor includes a first layer and a second layer,

the first layer is provided on the major surface of the substrate, and

the second layer is provided on the first layer.

5. The semiconductor device according to claim 4, wherein

a thermal expansion coefficient of the first layer is nearer to a thermal expansion coefficient of the substrate than is a thermal expansion coefficient of the second layer.

6. The semiconductor device according to claim 1, wherein

the plate conductor includes a first layer and a second layer,

the first layer is provided from the major surface of the substrate to the upper surface of the stacked body,

the first layer has a recess provided from the upper surface of the stacked body toward the major surface of the substrate, the recess extending in the first direction, and

the second layer is provided inside the recess.

7. The semiconductor device according to claim 6, wherein

a thermal expansion coefficient of the first layer is nearer to a thermal expansion coefficient of the substrate than is a thermal expansion coefficient of the second layer.

8. The semiconductor device according to claim 1, wherein

the columnar portion includes a fourth portion, a fifth portion, and a sixth portion along the stacking direction of the stacked body,

the sixth portion is provided between the fourth portion and the fifth portion,

a width of the fourth portion along the second direction is narrower than a width of the sixth portion along the second direction, and

a width of the fifth portion along the second direction is narrower than the width of the sixth portion along the second direction.

9. The semiconductor device according to claim 1, wherein

the stacked body includes a memory cell array, a first stairstep portion, and a second stairstep portion,

the first stairstep portion and the second stairstep portion are respectively provided along one set of opposite sides of the memory cell array, and

the plate portion is provided to cross through the memory cell array from the first stairstep portion to the second stairstep portion.

10. A semiconductor device, comprising:

a substrate having a major surface;

a stacked body provided on a major surface of the substrate, the stacked body including a plurality of electrode layers stacked with an insulator interposed, the stacked body including a lower layer portion, an upper layer portion, and a middle portion along a stacking direction of the stacked body, the middle portion being provided between the lower layer portion and the upper layer portion;

a first plate portion provided inside the stacked body, the first plate portion extending along the stacking direction of the stacked body and along a first direction orthogonal to the stacking direction, the first plate portion including a first plate conductor and a first sidewall insulating film, the first sidewall insulating film being provided between the first plate conductor and the stacked body;

a second plate portion provided to be separated from the first plate portion inside the stacked body, the second plate portion extending along the stacking direction of the stacked body and along the first direction, the second plate portion including a second plate conductor and a second sidewall insulating film, the second sidewall insulating film being provided between the second plate conductor and the stacked body; and

a columnar portion provided inside the stacked body, the columnar portion extending along the stacking direction of the stacked body, the columnar portion being provided between the first plate portion and the second plate portion, the columnar portion including a semiconductor body and a memory film, the memory film being provided between the semiconductor body and the electrode layers, the memory film including a charge storage portion inside the film,

a width of the electrode layer of the lower layer portion along a second direction being wider than a width of the electrode layer of the middle portion along the second direction, the second direction being orthogonal to the first direction along the major surface of the substrate,

a width of the electrode layer of the upper layer portion along the second direction being wider than the width of the middle portion along the second direction.

11. The semiconductor device according to claim 10, wherein

the lower layer portion includes a first electrode layer,

the upper layer portion includes a second electrode layer,

the middle portion includes a third electrode layer,

the first electrode layer is most proximal to the major surface of the substrate,

the second electrode layer is most distal to the major surface of the substrate, and

the third electrode layer is provided between the first electrode layer and the second electrode layer.

12. The semiconductor device according to claim 10, wherein

a width of the plurality of electrode layers along the second direction

becomes narrower along the stacking direction of the stacked body from the major surface of the substrate toward the middle portion, and

becomes wider along the stacking direction of the stacked body from the middle portion toward an upper surface of the stacked body.

13. The semiconductor device according to claim 10, wherein

the first plate conductor includes a first layer and a second layer,

the second plate conductor includes a third layer and a fourth layer,

the first layer and the third layer are provided on the major surface of the substrate,

the second layer is provided on the first layer, and

the fourth layer is provided on the third layer.

14. The semiconductor device according to claim 13, wherein thermal expansion coefficients of the first layer and the third layer are nearer to a thermal expansion coefficient of the substrate than are thermal expansion coefficients of the second layer and the fourth layer.

15. The semiconductor device according to claim 10, wherein

the first plate conductor includes a first layer and a second layer,

the second plate conductor includes a third layer and a fourth layer,

the first layer and the third layer are provided from a major surface of the substrate to an upper surface of the stacked body,

the first layer has a first recess provided from the upper surface of the stacked body toward the major surface of the substrate, the first recess extending in the first direction,

the third layer has a second recess provided from the upper surface of the stacked body toward the major surface of the substrate, the second recess extending in the first direction,

the second layer is provided inside the first recess, and

the fourth layer is provided inside the second recess.

16. The semiconductor device according to claim 13, wherein thermal expansion coefficients of the first layer and the third layer are nearer to a thermal expansion coefficient of the substrate than are thermal expansion coefficients of the second layer and the fourth layer.

17. The semiconductor device according to claim 10, wherein

the columnar portion includes a fourth portion, a fifth portion, and a sixth portion along the stacking direction of the stacked body,

the sixth portion is provided between the fourth portion and the fifth portion,

a width of the fourth portion along the second direction is narrower than a width of the sixth portion along the second direction, and

a width of the fifth portion along the second direction is narrower than the width of the sixth portion along the second direction.

18. The semiconductor device according to claim 10, wherein

the stacked body includes a memory cell array, a first stairstep portion, and a second stairstep portion,

the first stairstep portion and the second stairstep portion respectively are provided along one set of opposite sides of the memory cell array, and

the first plate portion and the second plate portion are provided to cross through the memory cell array from the first stairstep portion to the second stairstep portion.