HORIZONTAL GATE ALL AROUND NANOWIRE TRANSISTOR BOTTOM ISOLATION
First Claim
1. A method comprising:
- providing a substrate having source, drain and channel regions for a GAA MOSFET, the substrate doped with one of a p-type and an n-type dopant;
disposing an etch stop-electric well (ESEW) layer over an entire top surface of the substrate in the channel region, the ESEW layer doped with the other of the p-type and the n-type dopant;
disposing a sacrificial layer over an entire top surface of the ESEW layer such that the sacrificial layer is separated from the substrate by the ESEW layer in the channel region, the sacrificial layer doped with the same type dopant as the substrate;
disposing a channel layer over an entire top surface of the sacrificial layer in the channel region;
patterning a fin out of the ESEW layer, sacrificial layer, and channel layer in the channel region; and
selectively etching away only the sacrificial layer of the fin to form a nanowire from the channel layer of the fin while the ESEW layer of the fin functions as an etch stop barrier to prevent etching of trenches in the channel region of the substrate.
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Accused Products
Abstract
A method of forming a GAA MOSFET includes providing a substrate having source, drain and channel regions, the substrate doped with one of a p-type and an n-type dopant. Disposing an etch stop-electric well (ESEW) layer over the substrate, the ESEW layer doped with the other of the p-type and the n-type dopant. Disposing a sacrificial layer over the ESEW layer, the sacrificial layer doped with the same type dopant as the substrate. Disposing a channel layer over the sacrificial layer. Patterning a fin out of the ESEW layer, sacrificial layer and channel layer in the channel region. Selectively etching away only the sacrificial layer of the fin to form a nanowire from the channel layer of the fin while the ESEW layer of the fin functions as an etch stop barrier to prevent etching of trenches in the substrate.
18 Citations
20 Claims
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1. A method comprising:
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providing a substrate having source, drain and channel regions for a GAA MOSFET, the substrate doped with one of a p-type and an n-type dopant; disposing an etch stop-electric well (ESEW) layer over an entire top surface of the substrate in the channel region, the ESEW layer doped with the other of the p-type and the n-type dopant; disposing a sacrificial layer over an entire top surface of the ESEW layer such that the sacrificial layer is separated from the substrate by the ESEW layer in the channel region, the sacrificial layer doped with the same type dopant as the substrate; disposing a channel layer over an entire top surface of the sacrificial layer in the channel region; patterning a fin out of the ESEW layer, sacrificial layer, and channel layer in the channel region; and selectively etching away only the sacrificial layer of the fin to form a nanowire from the channel layer of the fin while the ESEW layer of the fin functions as an etch stop barrier to prevent etching of trenches in the channel region of the substrate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A GAA MOSFET comprising:
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a substrate doped with one of an n-type and a p-type dopant; an etch stop-electric well (ESEW) layer disposed over the substrate, the ESEW layer doped with the other of the n-type and p-type dopant and composed of a different material than the substrate; a source, drain and channel region disposed over the ESEW layer, the channel region having a nanowire channel connected between the source and drain regions; a gate dielectric coating disposed over the nanowire channel and the ESEW layer in the channel region; a gate metal disposed over the gate dielectric coating in the channel region to form a gate electrode of the GAA MOSFET; and wherein the ESEW layer is free of any trenches under the nanowire channel. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification