Compute Through Power Loss Hardware Approach For Processing Device Having Nonvolatile Logic Memory

• US 20170185139A1
• Filed: 02/05/2016
• Published: 06/29/2017
• Est. Priority Date: 12/29/2015
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Zwerg, Michael, Khanna, Sudhanshu, Bartling, Steven Craig
• Granted Patent: US 10,331,203 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 1/3293 by switching to a less power-consuming processor, e.g. sub-CPU
• CPC Class Codes: G06F 11/07 Responding to the occurrence of a fault, e.g. fault tolerance
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0625 Power saving in storage systems
• CPC Class Codes: G06F 3/0634 by changing the state or mode of one or more devices
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0656 Data buffering arrangements
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management
• CPC Class Codes: Y02D 30/50 in wire-line communication networks, e.g. low power modes or reduced link rate

Abstract

A computing device apparatus facilitates use of a deep low power mode that includes powering off the device'"'"'s CPU by including a hardware implemented process to trigger storage of data from the device'"'"'s volatile storage elements in non-volatile memory in response to entering the low power mode. A hardware based power management unit controls the process including interrupting a normal processing order of the CPU and triggering the storage of the data in the non-volatile memory. In response to a wake-up event, the device is triggered to restore the data stored in the non-volatile memory to the volatile memory prior to execution of a wake up process for the CPU from the low power mode. The device includes a power storage element such as a capacitor that holds sufficient energy to complete the non-volatile data storage task prior to entering the low power mode.

Claims

1. A computing device apparatus comprising:

a central processing unit;

a power management unit configured to detect multiple levels of available power for the central processing unit and to effect switching power on or off for the central processing unit;

an energy storage unit connected to provide power to the computing device apparatus and configured to hold enough energy to operate the computing device apparatus after removal of power from the computing device apparatus;

a non-volatile memory;

a non-volatile memory controller configured to control the non-volatile memory and have direct access to volatile storage elements embedded in or associated with one or more of the central processing unit or one or more peripherals;

wherein the power management unit is configured to;

interrupt a normal processing order of the central processing unit to effect entry of the central processing unit into a low power mode in response to detecting a power loss event initiated by the power management unit due to detection of a power loss scenario or initiated by the central processing unit to save energy,

use energy stored in the energy storage device to;

in response to entering into the low power mode, trigger the non-volatile memory controller to store data stored in the volatile storage elements in the non-volatile memory, the data representing a state of the one or more of the central processing unit or one or more peripherals, and

after the data is saved in the non-volatile memory, effect switching off power to at least the central processing unit,

during the low power mode state, detect restoration of power to the computing device apparatus or a wakeup request from the central computing unit'"'"'s power off state,

in response to detecting the restoration of power or the wakeup request, trigger the non-volatile memory controller to restore the data to the volatile storage elements from the non-volatile memory prior to execution of a wake up process for the central processing unit from the low power mode.

2. The computing device apparatus of claim 1 wherein the non-volatile memory has a high write cycle endurance of 10¹⁰.

3. The computing device apparatus of claim 1, wherein the non-volatile memory controller is configured to not store bus interface state information for the central processing unit in response to entering the low power mode.

4. The computing device apparatus of claim 1, wherein the non-volatile memory controller is configured to not store serial communication module information for the central processing unit in response to entering the low power mode.

5. The computing device apparatus of claim 1, wherein the non-volatile memory controller is configured to not store state machine information for the central processing unit in response to entering the low power mode.

6. The computing device apparatus of claim 1, wherein the non-volatile memory controller is configured to not store pipeline register information for the central processing unit or the one or more peripherals in response to entering the low power mode.

7. The computing device apparatus of claim 1, wherein the central processing unit and the power management unit are configured to not automatically trigger execution of a cold boot initialization process in response to the detecting the restoration of power or the wake up request.

8. The computing device apparatus of claim 1, wherein the non-volatile memory controller is configured to effect storing the data of the central processing unit by storing one or more of program counters, stack pointers, status registers, general purpose registers, or other key state information of the central processing unit.

9. The computing device apparatus of claim 1, wherein the non-volatile memory controller is configured to effect storing the data of the one or more peripherals associated with the central processing unit by storing one or more of peripheral configuration registers, peripheral state registers, peripheral status registers, peripheral data buffers, and other key peripheral state information.

10. The computing device apparatus of claim 1, wherein the power management unit is configured to prevent a startup of the computing device apparatus unless enough energy is present on the energy storage unit to complete a round trip restore and save operation.

11. A method of hardware based control of entering and exiting a low power mode for a computing device, the method comprising:

a computing device operating in a normal mode of operation, the computing device having a central processing unit and peripherals using volatile storage elements;

using hardware of the computing device including a power management unit to detect a low power event for the processing device, the low power event initiated by the power management unit due to detection of a power loss scenario or initiated by the central processing unit to save energy;

in response to detecting the low power event, using energy stored in an energy storage device for the computing device to control entry into a low power mode for the computing device including by;

triggering a non-volatile memory controller to store data stored in the volatile storage elements in a non-volatile memory having direct access to the volatile storage elements, the data representing a state of one or more of the central processing unit or one or more of the peripherals,

after the data is saved, switching off power to at least the central processing unit,

during the low power mode state, detecting by the power management unit restoration of power to the computing device apparatus or a wakeup request from the central computing unit'"'"'s power off state;

in response to detecting the restoration of power or the wake up request, triggering the non-volatile memory controller to restore the data to the volatile storage elements from the non-volatile memory prior to execution of a wake up process for the central processing unit from the low power mode.

12. The method of claim 11 wherein the storing the low power state of the central processing unit at the low power mode in the non-volatile memory having a high write cycle endurance of at least 10¹⁰.

13. The method of claim 11, further comprising not storing bus interface state information for the central processing unit in response to entering the low power mode.

14. The method of claim 11, further comprising not storing serial communication module information for the central processing unit in response to entering the low power mode.

15. The method of claim 11, further comprising not storing state machine information for the central processing unit in response to entering the low power mode.

16. The method of claim 11, further comprising not storing pipeline register information for the central processing unit or the peripherals in response to detection of the loss of power sufficient to support the low power mode.

17. The method of claim 11, further comprising not automatically triggering execution of a cold boot initialization process in response to the detecting the restoration of power or the wake up request.

18. The method of claim 11, further comprising preventing a startup of the computing device apparatus unless enough energy is present on the energy storage unit to complete a round trip restore and save operation.