MEMORY SYSTEM AND OPERATING METHOD OF MEMORY SYSTEM

• US 20170185295A1
• Filed: 05/18/2016
• Published: 06/29/2017
• Est. Priority Date: 12/23/2015
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: BYUN, Eu-Joon
• Granted Patent: US 10,073,628 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0616 in relation to life time, e.g. increasing Mean Time Between Failures [MTBF]
• CPC Class Codes: G06F 3/0626 Reducing size or complexity of storage systems
• CPC Class Codes: G06F 3/064 Management of blocks
• CPC Class Codes: G06F 3/0647 Migration mechanisms
• CPC Class Codes: G06F 3/0652 Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays

Abstract

The memory system, may include: a memory device comprising a plurality of memory blocks; and a controller suitable for performing a command operation to the memory blocks, updating update parameters and erase cycles (ECs) of the memory blocks, selecting at least one source memory block based on the update parameters, selecting at least one target memory block based on the ECs, and performing at least one swap operation between the selected at least one or more source memory block and the selected at least one target memory block.

Claims

1. A memory system, comprising:

a memory device comprising a plurality of memory blocks; and

a controller suitable for performing a command operation to the memory blocks, updating update parameters and erase cycles (ECs) of the memory blocks, selecting at least one source memory block based on the update parameters, selecting at least one target memory block based on the ECs, and performing at least one swap operation between the selected at least one or more source memory block and the selected at least one target memory block.

2. The memory system of claim 1, wherein the controller selects first and second source memory blocks having highest and lowest update parameter values among the memory blocks, respectively;

and

selects first and second target memory blocks having highest and lowest EC values among the memory blocks, respectively.

3. The memory system of claim 2,

wherein the controller further performs a first swap operation between the first source memory block and the second target memory block, and

a second swap operation between the second source memory block and the first target memory block.

4. The memory system of claim 3,

wherein the command operation is at least one of an update read operation and an update program operation to the memory blocks, and

wherein the controller updates the update parameters of the memory blocks in an update list as a result of the command operation.

5. The memory system of claim 4,

wherein the command operation is an erase operation to the memory blocks, and

wherein the controller updates the ECs of the memory blocks in an erase list as a result of the command operation.

6. The memory system of claim 5, wherein the controller stores the update list and the erase list in a memory included therein.

7. An operating method of a memory system including a plurality of memory blocks, comprising:

performing a command operation to the memory blocks;

updating update parameters and erase cycles (ECs) of the memory blocks as a result of the command operation; and

selecting at least one source memory block and at least one target memory block from the memory blocks for a wear leveling operation based on the update parameters and the ECs, respectively.

8. The operating method of claim 7, wherein the selecting of the at least one source memory block and the at least one target memory block comprises:

selecting first and second source memory blocks having highest and lowest update parameter values among the memory blocks, respectively; and

selecting first and second target memory blocks having highest and lowest EC values among the memory blocks, respectively.

9. The operating method of claim 8, further comprising:

performing a first swap operation between the first source memory block and the second target memory block; and

performing a second swap operation between the second source memory block and the first target memory block.

10. The operating method of claim 8,

wherein the command operation is at least one of an update read operation, and an update program operation to the memory blocks, and

wherein the update parameters of the memory blocks and are updated as a result of the command operation.

11. The operating method of claim 8,

wherein the command operation is an erase operation to the memory blocks, and

wherein the ECs of the memory blocks are updated as a result of the command operation.

12. The operating method of claim 11, further comprising storing the updated update parameters list and the erase list in an update list and an EC list in a memory included in the controller of the memory system.