NON-VOLATILE MEMORY SERIAL CORE ARCHITECTURE

• US 20170185297A1
• Filed: 01/06/2017
• Published: 06/29/2017
• Est. Priority Date: 11/27/2006
• Status: Active Grant

• Current Assignee: MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management)
• Original Assignee: Conversant Intellectual Property Management Inc (MOSAID Technologies Inc. (f/k/a Conversant Intellectual Property Management))
• Inventors: KIM, Jin-Ki
• Granted Patent: US 10,007,439 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 3/061 Improving I/O performance
• CPC Class Codes: G06F 3/0629 Configuration or reconfiguration of storage systems
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0679 Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/08 Address circuits; Decoders; Word-line control circuits
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/16 for erasing blocks, e.g. arrays, words, groups
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 2207/107 Serial-parallel conversion of data or prefetch
• CPC Class Codes: G11C 2216/14 Circuits or methods to write a page or sector of information simultaneously into a nonvolatile memory, typically a complete row or word line in flash memory
• CPC Class Codes: G11C 2216/20 Suspension of programming or erasing cells in an array in order to read other cells in it
• CPC Class Codes: G11C 2216/30 Reduction of number of input/output pins by using a serial interface to transmit or receive addresses or data, i.e. serial access memory
• CPC Class Codes: G11C 5/025 Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device geometrical lay-out of the components in integrated circuits, H01L27/0207
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1033 using data registers of which only one stage is addressed for sequentially outputting data from a predetermined number of stages, e.g. nibble read-write mode
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1042 : using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
• CPC Class Codes: G11C 7/1048 : Data bus control circuits, e.g. precharging, presetting, equalising
• CPC Class Codes: G11C 7/1051 : Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1072 : for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/12 : Bit line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down circuits, precharging circuits, equalising circuits, for bit lines

Abstract

A memory system having a serial data interface and a serial data path core for receiving data from and for providing data to at least one memory bank as a serial bitstream. The memory bank is divided into two halves, where each half is divided into upper and lower sectors. Each sector provides data in parallel to a shared two-dimensional page buffer with an integrated self column decoding circuit. A serial to parallel data converter within the memory bank couples the parallel data from either half to the serial data path core. The shared two-dimensional page buffer with the integrated self column decoding circuit minimizes circuit and chip area overhead for each bank, and the serial data path core reduces chip area typically used for routing wide data buses. Therefore a multiple memory bank system is implemented without a significant corresponding chip area increase when compared to a single memory bank system having the same density.

Claims

1. A non-volatile memory system comprising:

at least one non-volatile memory device; and

a memory controller communicatively coupled to the least one non-volatile memory device, the memory controller configured to provide to the at least one non-volatile memory device a chip select signal, a clock signal, and at least one common data signal carrying command data, address data and write data,

the at least one non-volatile memory device comprising;

a plurality of non-volatile memory banks,

a chip select input configured to receive the chip select signal for enabling the non-volatile memory banks,

a clock input configured to receive the clock signal for synchronizing the at least one common data signal, and

at least one common data input configured to receive the at least one common data signal for providing the command data, the address data and the write data to the non-volatile memory banks,

wherein each non-volatile memory bank comprises;

a first non-volatile memory sector having non-volatile memory cells coupled to first bitlines and first wordlines, the first bitlines being arranged as m segments where m is an integer value greater than 0,

a second non-volatile memory sector having non-volatile memory cells coupled to second bitlines and second wordlines, the second bitlines being arranged as m segments, and

a page buffer disposed between the first non-volatile memory sector and the second non-volatile memory sector for selectively coupling one of the first bitlines and the second bitlines of each of the m segments to a predetermined number of data lines, the predetermined number of data lines containing at least a portion of the write data.

2. The non-volatile memory system of claim 1, wherein the page buffer comprises:

a first self-decoding page buffer stage for sensing data from a first bitline, and for providing sensed data corresponding to the first bitline on a corresponding data line in response to an active column select bit latched in a clock signal state, the first self-decoding page buffer stage including an output terminal for providing the active column select bit; and

a second self-decoding page buffer stage having an input terminal for receiving the active column select bit from the output terminal of the first self-decoding page buffer stage, for sensing data from a second bitline, and providing sensed data corresponding to the second bitline on the corresponding data line in response to the active column select bit latched in a subsequent clock signal state.

3. The non-volatile memory system of claim 2, wherein the page buffer is configured to perform a self-decoding operation, the self-decoding operation comprising:

latching the active column select bit in the first self-decoding page buffer stage in response to an opposite clock signal state, the opposite clock signal state being complementary to the clock signal state,

providing the sensed data from the first self-decoding page buffer stage and passing the active column select bit in response to the clock signal state,

latching the active column select bit in the second self-decoding page buffer stage in response to a subsequent opposite clock signal state, and

providing the sensed data from the second self-decoding page buffer stage in response to the subsequent clock signal state.

4. The non-volatile memory system of claim 1, wherein each non-volatile memory bank further comprises common bitlines coupled to the page buffer, each of the common bitlines coupled to at least one segment of the first bitlines and to at least one segment of the second bitlines.

5. The memory bank of claim 4, wherein the common bitlines are grouped as a first set of common bitlines and a second set of common bitlines.