SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME

• US 20170186851A1
• Filed: 03/13/2017
• Published: 06/29/2017
• Est. Priority Date: 04/12/2013
• Status: Active Grant

• Current Assignee: Sumitomo Electric Device Innovations Incorporated (Sumitomo Corporation)
• Original Assignee: Sumitomo Electric Device Innovations Incorporated (Sumitomo Corporation)
• Inventors: Nishi, Masahiro
• Granted Patent: US 10,446,661 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/28587 characterised by the sectional shape, e.g. T, inverted T
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/3083 characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
• CPC Class Codes: H01L 29/2003 Nitride compounds
• CPC Class Codes: H01L 29/205 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/66462 with a heterojunction interface channel or gate, e.g. HFET, HIGFET, SISFET, HJFET, HEMT
• CPC Class Codes: H01L 29/7787 with wide bandgap charge-carrier supplying layer, e.g. direct single heterostructure MODFET

Abstract

A semiconductor device includes a semiconductor layer formed on a substrate, an electrode contact window that includes a recess formed on a surface of the semiconductor layer, an inner wall having a slope, and a source electrode, a drain electrode, and a gate electrode formed on the semiconductor layer, in which the drain electrode is in contact with the slope of the inner wall.

Claims

1. -17. (canceled)

18. A semiconductor device comprising:

a semiconductor layer formed on a substrate, the semiconductor layer including an electron transit layer on the substrate, an electron supply layer on the electron transit layer, and a cap layer on the electron supply layer;

an electrode contact window that includes a recess formed in the electron supply layer and the cap layer, an inner wall of the recess having a slanted slope, wherein the electron supply layer and the cap layer are exposed in the inner wall of the electrode contact window; and

a source electrode, a drain electrode, and a gate electrode formed on the semiconductor layer,

wherein the drain electrode is formed in the recess.

19. The semiconductor device according to claim 18,

wherein the recess includes an edge,

wherein the edge of the recess is located at the surface of the cap layer, and

wherein the slanted slope extends from the bottom to the edge.

20. The semiconductor device according to claim 18,

wherein the electron supply layer includes AlGaN or InAlN, and the cap layer includes GaN, and

wherein the slanted slope traverses between the electron supply layer and the cap layer.

21. The semiconductor device according to claim 18,

wherein the drain electrode extends to a top surface of the semiconductor layer.

22. The semiconductor device according to claim 18,

wherein a bottom of the recess is formed in the electron supply layer.

23. The semiconductor device according to claim 18,

wherein the drain electrode extends to the cap layer exposed on the inner wall.

24. The semiconductor device according to claim 18,

wherein the semiconductor layer includes a nitride semiconductor layer.

25. The semiconductor device according to claim 18,

wherein a width of the inner wall in a direction horizontal to a surface of the substrate is equal to or greater than 0.03 μ

m and equal to or smaller than 0.1 μ

m.

26. The semiconductor device according to claim 18,

wherein the semiconductor layer includes a doping region containing dopant, and wherein the recess is formed in the doping region.

27. The semiconductor device according to claim 18, further comprising a passivation layer formed on the slanted slope, the source electrode, and the drain electrode, wherein the gate electrode is located in an opening formed in the passivation layer.

28. A semiconductor device comprising:

a semiconductor layer formed on a substrate, the semiconductor layer including an electron transit layer on the substrate, an electron supply layer on the electron transit layer, and a cap layer on the electron supply layer;

an electrode contact window that includes a recess formed in the electron supply layer and the cap layer, an inner wall of the recess having a slanted slope and a bottom wherein the bottom is formed in the electron supply layer; and

a source electrode, a drain electrode, and a gate electrode formed on the semiconductor layer,

wherein the drain electrode is formed in the recess.

29. The semiconductor device according to claim 28,

wherein the recess includes an edge,

wherein the edge of the recess is located at the surface of the cap layer, and

wherein the slanted slope extends from the bottom to the edge.

30. The semiconductor device according to claim 28,

wherein the electron supply layer includes AlGaN or InAlN, and the cap layer includes GaN, and

wherein the slanted slope traverses between the electron supply layer and the cap layer.

31. The semiconductor device according to claim 28,

wherein the drain electrode extends to a top surface of the semiconductor layer.

32. The semiconductor device according to claim 28,

wherein at least one of the electron supply layer and the cap layer are exposed at the inner wall of the electrode contact window.

33. The semiconductor device according to claim 32,

wherein the drain electrode extends to the cap layer exposed on the inner wall.

34. The semiconductor device according to claim 28,

wherein the semiconductor layer includes a nitride semiconductor layer.

35. The semiconductor device according to claim 28,

wherein a width of the inner wall in a direction horizontal to a surface of the substrate is equal to or greater than 0.03 μ

m and equal to or smaller than 0.1 μ

m.

36. The semiconductor device according to claim 28,

wherein the semiconductor layer includes a doping region containing dopant, and

wherein the recess is formed in the doping region.

37. The semiconductor device according to claim 28, further comprising a passivation layer formed on the slanted slope, the source electrode, and the drain electrode, wherein the gate electrode is located in an opening formed in the passivation layer.