Method of Producing an Integrated Power Transistor Circuit Having a Current-Measuring Cell
First Claim
1. A method for producing an integrated power transistor circuit, the method comprising:
- forming at least one transistor cell in a cell array, each transistor cell having a doped region formed in a semiconductor substrate and adjoining a first surface of the semiconductor substrate on a first side of the semiconductor substrate;
depositing a contact layer on the first side;
structuring the contact layer to form a contact structure from the contact layer, the contact structure having, in a projection of the cell array orthogonal to the first surface, a first section and, outside the cell array, a second section which connects the first section to an interface structure; and
forming an electrode structure on and in direct contact with the first section in the orthogonal projection of the cell array, the electrode structure being absent outside the cell array.
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Accused Products
Abstract
A method for producing an integrated power transistor circuit includes forming at least one transistor cell in a cell array, each transistor cell having a doped region formed in a semiconductor substrate and adjoining a first surface of the semiconductor substrate on a first side of the semiconductor substrate, depositing a contact layer on the first side, structuring the contact layer to form a contact structure from the contact layer, the contact structure having, in a projection of the cell array orthogonal to the first surface, a first section and, outside the cell array, a second section which connects the first section to an interface structure, and forming an electrode structure on and in direct contact with the first section in the orthogonal projection of the cell array, the electrode structure being absent outside the cell array.
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Citations
19 Claims
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1. A method for producing an integrated power transistor circuit, the method comprising:
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forming at least one transistor cell in a cell array, each transistor cell having a doped region formed in a semiconductor substrate and adjoining a first surface of the semiconductor substrate on a first side of the semiconductor substrate; depositing a contact layer on the first side; structuring the contact layer to form a contact structure from the contact layer, the contact structure having, in a projection of the cell array orthogonal to the first surface, a first section and, outside the cell array, a second section which connects the first section to an interface structure; and forming an electrode structure on and in direct contact with the first section in the orthogonal projection of the cell array, the electrode structure being absent outside the cell array. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method for producing an integrated power transistor circuit, the method comprising:
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forming a plurality of transistor cells of a cell array connected in parallel to form a power transistor, each of the transistor cells having a doped region formed in a semiconductor substrate and adjoining a first surface on a first side of the semiconductor substrate, a channel region and a gate conductor structure; forming an electrode structure on the first side of the semiconductor substrate in a projection of the cell array orthogonal to the first surface; forming a gate electrode on the first side of the semiconductor substrate outside the cell array, the gate electrode being physically separated from and electrically connected to each gate conductor structure, wherein each gate conductor structure extends in a longitudinal direction from the cell array into a region outside the cell array and under the gate electrode; forming a contact structure on the first side of the semiconductor substrate and electrically conductively connected to the doped region and the electrode structure, the contact structure having a first section between the electrode structure and the semiconductor substrate above the cell array, a second section above the region outside the cell array and connecting the first section to an interface structure in the region outside the cell array, and a third section arranged on the first side of the semiconductor substrate outside the cell array and between the gate electrode and the semiconductor substrate, the third section being electrically insulated and physically separated from the first and the second sections; forming a dielectric layer between the first surface and the contact structure in both the cell array and the region outside the cell array; and forming plated-through holes in the cell array which extend through the dielectric layer and electrically connect the contact structure to the doped region and the channel region of each transistor cell of the power transistor. - View Dependent Claims (8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19)
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Specification