Digitally controlled zero voltage switching

• US 20170187284A1
• Filed: 12/23/2015
• Published: 06/29/2017
• Est. Priority Date: 12/23/2015
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ravichandran, Krishnan, Vaidya, Vaibhav, Kumar, Pavan, De, Vivek K.
• Granted Patent: US 10,069,397 B2
• Time in Patent Office: Days
• CPC Class Codes: H02M 1/0012 Control circuits using digital or numerical techniques in DC/DC converters H02M3/157, H02M3/33515; in DC-AC converters H02M7/53873
• CPC Class Codes: H02M 1/0058 by employing soft switching techniques, i.e. commutation of transistors when applied voltage is zero or when current flow is zero using an auxiliary actively switched resonant commutation circuit connected to an intermediate DC voltage or between two push-pull branches of an inverter bridge H02M7/4811; in resonant inverters H02M7/4815; in inverters operating from a resonant DC source H02M7/4826
• CPC Class Codes: H02M 1/083 for the ignition at the zero crossing of the voltage or the current
• CPC Class Codes: H02M 1/38 Means for preventing simultaneous conduction of switches
• CPC Class Codes: H02M 3/1588 comprising at least one synchronous rectifier element H02M3/1582, H02M3/1584 take precedence
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

Generally, this disclosure describes an apparatus. The apparatus includes switch controller circuitry. The switch controller circuitry includes dead time logic circuitry to determine an estimated dead time interval between a turn off of a first switch and a turn on of a second switch. The first switch and the second switch are coupled at a switched node. The estimated dead time interval is determined based, at least in part, on a difference between an input voltage, Vin, and a switched voltage, Vsw, detected at the switched node just prior to turning off the first switch, a parasitic capacitance, Cpar, associated with the switched node and a maximum inductor current, I_L,max. The difference between Vin and Vsw represents the maximum inductor current.

Claims

1. An apparatus comprising:

switch controller circuitry to control a conduction state of a first switch and a second switch in a DC to DC converter; and

dead time logic circuitry to determine an estimated dead time interval between a turn off of the first switch and a turn on of the second switch, the first switch and the second switch coupled at a switched node, the estimated dead time interval determined based, at least in part, on a difference between an input voltage, Vin, and a switched voltage, Vsw, detected at the switched node just prior to turning off the first switch, a parasitic capacitance, Cpar, associated with the switched node and a maximum inductor current, I_L,max, the difference between Vin and Vsw representing the maximum inductor current.

2. The apparatus of claim 1, wherein the dead time logic circuitry comprises differential clocking circuitry and phase comparator circuitry, the differential clocking circuitry to receive the input voltage and the switched voltage as inputs and to provide a first clocked signal and a second clocked signal as outputs, a phase difference between the first clocked signal and the second clocked signal representing the difference between Vin and Vsw, the phase comparator circuitry to determine the phase difference.

3. The apparatus of claim 2, wherein the phase comparator circuitry comprises a first plurality of D flip flops and a second plurality of offset circuitries.

4. The apparatus of claim 1, wherein the dead time is determined as T=Cpar*Vin/I_L,max, and I_L,max corresponds to the maximum inductor current just prior to the first switch turning off, I_L,max estimated based, at least in part, on the difference between Vin and Vsw and the switch controller circuitry is to set a dead time to the estimate in a same PWM (pulse width modulation) cycle as the estimated dead time interval was determined.

5. The apparatus of claim 2, wherein an output of the phase comparator circuitry is a digital code corresponding to the phase difference.

6. The apparatus of claim 1, wherein the switch controller circuitry further comprises delay adjustment logic circuitry to determine whether the estimated dead time interval is greater than or less than an optimal dead time interval based, at least in part, on the switched voltage and based, at least in part, on a control input to the second switch.

7. The apparatus of claim 6, wherein the delay adjustment logic circuitry comprises a NOR gate to detect whether the estimated dead time interval is greater than the optimal dead time interval and an AND gate to detect whether the estimated time interval is less than the optimal dead time interval.

8. The apparatus of claim 3, wherein a respective delay time of at least some offset circuitries of the plurality of offset circuitries is a respective whole number multiple of a delay increment Δ

t.

9. The apparatus of claim 8, wherein the delay increment is related to a minimum resolution for the difference between Vin and Vsw.

10. A method comprising:

controlling, by switch controller circuitry, a conduction state of a first switch and a second switch in a DC to DC converter; and

determining, by dead time logic circuitry, an estimated dead time interval between a turn off of the first switch and a turn on of the second switch, the first switch and the second switch coupled at a switched node, the estimated dead time interval determined based, at least in part, on a difference between an input voltage, Vin, and a switched voltage, Vsw, detected at the switched node just prior to turning off the first switch, a parasitic capacitance, Cpar, associated with the switched node and a maximum inductor current, I_L,max, the difference between Vin and Vsw representing the maximum inductor current.

11. The method of claim 10, further comprising receiving, by differential clocking circuitry, the input voltage and the switched voltage as inputs;

providing, by the differential clocking circuitry, a first clocked signal and a second clocked signal as outputs; and

determining, by phase comparator circuitry, a phase difference between the first clocked signal and the second clocked signal, the phase difference representing the difference between Vin and Vsw.

12. The method of claim 11, wherein the phase comparator circuitry comprises a first plurality of D flip flops and a second plurality of offset circuitries.

13. The method of claim 10, further comprising setting, by the switch controller circuitry a dead time to the estimate in a same PWM (pulse width modulation) cycle as the estimated dead time interval was determined, the estimated dead time determined as T=Cpar*Vin/I_L,max, and IL,max corresponds to the maximum inductor current just prior to the first switch turning off, I_L,max estimated based, at least in part, on the difference between Vin and Vsw.

14. The method of claim 11, wherein an output of the phase comparator circuitry is a digital code corresponding to the phase difference.

15. The method of claim 10, further comprising determining, by delay adjustment logic circuitry, whether the estimated dead time interval is greater than or less than an optimal dead time interval based, at least in part, on the switched voltage and based, at least in part, on a control input to the second switch.

16. The method of claim 15, further comprising detecting, by a NOR gate, whether the estimated dead time interval is greater than the optimal dead time interval and detecting, by an AND gate, whether the estimated time interval is less than the optimal dead time interval.

17. The method of claim 12, wherein a respective delay time of at least some offset circuitries of the plurality of offset circuitries is a respective whole number multiple of a delay increment Δ

t.

18. A system comprising:

DC to DC converter circuitry;

switch controller circuitry to control a conduction state of a first switch and a second switch in a DC to DC converter; and

dead time logic circuitry to determine an estimated dead time interval between a turn off of the first switch and a turn on of the second switch, the first switch and the second switch coupled at a switched node, the estimated dead time interval determined based, at least in part, on a difference between an input voltage, Vin, and a switched voltage, Vsw, detected at the switched node just prior to turning off the first switch, a parasitic capacitance, Cpar, associated with the switched node and a maximum inductor current, I_L,max, the difference between Vin and Vsw representing the maximum inductor current.

19. The system of claim 18, wherein the dead time logic circuitry comprises differential clocking circuitry and phase comparator circuitry, the differential clocking circuitry to receive the input voltage and the switched voltage as inputs and to provide a first clocked signal and a second clocked signal as outputs, a phase difference between the first clocked signal and the second clocked signal representing the difference between Vin and Vsw, the phase comparator circuitry to determine the phase difference.

20. The system of claim 19, wherein the phase comparator circuitry comprises a first plurality of D flip flops and a second plurality of offset circuitries.

21. The system of claim 18, wherein the dead time is determined as T=Cpar*Vin/I_L,max, and I_L,max corresponds to the maximum inductor current just prior to the first switch turning off, I_L,max estimated based, at least in part, on the difference between Vin and Vsw and the switch controller circuitry is to set a dead time to the estimate in a same PWM (pulse width modulation) cycle as the estimated dead time interval was determined.

22. The system of claim 19, wherein an output of the phase comparator circuitry is a digital code corresponding to the phase difference.

23. The system of claim 18, wherein the switch controller circuitry further comprises delay adjustment logic circuitry to determine whether the estimated dead time interval is greater than or less than an optimal dead time interval based, at least in part, on the switched voltage and based, at least in part, on a control input to the second switch.

24. The system of claim 23, wherein the delay adjustment logic circuitry comprises a NOR gate to detect whether the estimated dead time interval is greater than the optimal dead time interval and an AND gate to detect whether the estimated time interval is less than the optimal dead time interval.

25. The system of claim 20, wherein, a respective delay time of at least some offset circuitries of the plurality of offset circuitries is a respective whole number multiple of a delay increment Δ

t.