ZERO CACHE MEMORY SYSTEM EXTENSION

• US 20170192896A1
• Filed: 12/31/2015
• Published: 07/06/2017
• Est. Priority Date: 12/31/2015
• Status: Abandoned Application

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Inventors: Seshadri, Vivek, Chilimbi, Trishul A, Ruwase, Olatunji
• Application Number:
  US14/986,470
• Publication Number:
  US 20170192896A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 12/0848 Partitioned cache, e.g. separate instruction and operand caches
• CPC Class Codes: G06F 12/0875 with dedicated cache, e.g. instruction or stack
• CPC Class Codes: G06F 12/0888 using selective caching, e.g. bypass
• CPC Class Codes: G06F 12/0893 Caches characterised by their organisation or structure
• CPC Class Codes: G06F 12/128 adapted to multidimensional cache systems, e.g. set-associative, multicache, multiset or multilevel
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/1044 Space efficiency improvement
• CPC Class Codes: G06F 2212/1048 Scalability
• CPC Class Codes: G06F 2212/401 Compressed data
• CPC Class Codes: G06F 2212/452 Instruction code
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/30192 according to data descriptor, e.g. dynamic data typing
• CPC Class Codes: G06F 9/381 Loop buffering
• CPC Class Codes: G06F 9/3836 Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
• CPC Class Codes: G06N 3/08 Learning methods

Abstract

A zero cache memory system extension includes a zero cache to store cache tags associated with zero cache lines, while a corresponding data cache stores cache tags and data bytes associated with non-zero cache lines. As non-zero data is written to the cache, cache lines may be moved from the zero cache to the data cache. Similarly, as zero data is written to the cache, cache lines may be moved from the data cache to the zero cache.

Claims

1. A device comprising:

a processor;

a memory communicatively coupled to the processor; and

a cache system communicatively coupled to the processor and the memory, wherein the cache system includes;

a data cache configured to store cache tags and data bytes associated with cache lines that include at least one non-zero value; and

a zero cache configured to store cache tags associated with zero cache lines.

2. A device as recited in claim 1, wherein the data cache and the zero cache are mutually exclusive such that a particular data value is stored in a single one of the data cache or the zero cache.

3. A device as recited in claim 1, wherein the cache system is configured to:

receive from the processor, a read instruction; and

send the read instruction to both the data cache and the zero cache.

4. A device as recited in claim 1, wherein the cache system is configured to:

receive from the processor, an instruction to write a first non-zero value to the cache system;

determine a value in the cache system that is to be replaced by the first non-zero value; and

when the value in the cache system to be replaced is a second non-zero value in the data cache, execute the write instruction against the data cache to replace the second non-zero value in the data cache with the first non-zero value.

5. A device as recited in claim 1, wherein the cache system is configured to:

receive from the processor, an instruction to write a non-zero value to the cache system;

determine a value in the cache system that is to be replaced by the non-zero value; and

when the value in the cache system to be replaced is a zero value in the data cache, execute the write instruction against the data cache to replace the zero value in the data cache with the non-zero value.

6. A device as recited in claim 1, wherein the cache system is configured to:

receive from the processor, an instruction to write a non-zero value to the cache system;

determine a value in the cache system that is to be replaced by the non-zero value; and

when the value in the cache system to be replaced is a zero value in the zero cache;

delete from the zero cache, a cache line containing the zero value to be replaced;

write to the data cache, the cache line containing the zero value to be replaced; and

execute the write instruction against the data cache to replace the zero value that was in the zero cache with the non-zero value.

7. A device as recited in claim 1, wherein the cache system is configured to:

receive from the processor, an instruction to write a zero value to the cache system;

determine a value in the cache system that is to be replaced by the zero value; and

when the value in the cache system to be replaced is a non-zero value in the data cache, execute the write instruction against the data cache to replace the non-zero value in the data cache with the zero value.

8. A device as recited in claim 7, wherein when the value in the cache system to be replaced is a non-zero value in the data cache, the cache system is further configured to:

examine a cache line in the data cache that includes the zero value; and

when the cache line in the data cache that includes the zero value includes other zero values and does not include a non-zero value;

write to the zero cache, cache tags corresponding to the cache line containing the zero value in the data cache; and

delete from the data cache, the cache line containing the zero value.

9. A method comprising:

receiving from a processor, a read request;

sending the read request to a data cache that stores cache lines that include non-zero data;

sending the read request to a zero cache that stores zero cache lines; and

in an event that the read request is satisfied by zero data in the zero cache, returning to the processor, an indication of a zero cache hit from the zero cache.

10. A method as recited in claim 9, further comprising:

receiving from the processor, a cache write instruction;

determining whether the cache write instruction is to write zero data; and

when the cache write instruction is to write zero data and the zero data is to replace non-zero data;

writing the zero data to the data cache to replace the non-zero data;

examining, in the data cache, a cache line that includes the zero data; and

when the cache line that includes the zero data does not include any non-zero data;

adding a cache tag to the zero cache to represent the cache line; and

removing from the data cache, the cache line that includes the zero data.

11. A method as recited in claim 10, further comprising:

when the write instruction is to write non-zero data and the non-zero data is to replace zero data in the zero cache;

identifying a cache line in the zero cache that includes the zero data to be replaced;

adding to the data cache, a cache tag and zero data corresponding to the cache line in the zero cache;

removing from the zero cache, the cache line that includes the zero data to be replaced; and

writing the non-zero data to the data cache.

12. A system configured to perform the method as recited in claim 9, wherein the system comprises:

the processor; and

a cache system communicatively coupled to the processor, wherein the cache system includes;

the data cache; and

the zero cache.

13. A system comprising:

means for processing; and

means for caching, wherein the means for caching includes;

means for caching non-zero data, the means for caching non-zero data communicatively coupled to the processor; and

means for caching zero data, the means for caching zero data communicatively coupled to the processor.

14. A system as recited in claim 13, wherein the means for caching non-zero data and the means for caching zero data are mutually exclusive such that a particular data value is cached in a single one of the means for caching non-zero data or the means for caching zero data.

15. A system as recited in claim 13, wherein the means for caching is configured to:

receive a read request from the means for processing; and

in response to receiving the read request;

send the read request to the means for caching non-zero data; and

substantially simultaneously, send the read request to the means for caching zero data.

16. A system as recited in claim 13, wherein the means for caching is configured to:

receive from the means for processing, an instruction to write a first non-zero value;

determine a value that is to be replaced by the first non-zero value; and

when the value to be replaced is a second non-zero value in the means for caching non-zero data, executing the write instruction against the means for caching non-zero data to replace the second non-zero value with the first non-zero value.

17. A system as recited in claim 13, wherein the means for caching is configured to:

receive from the means for processing, an instruction to write a non-zero value;

determine a value to be replaced by the non-zero value; and

when the value to be replaced is a zero value in the means for caching non-zero data, executing the write instruction to replace the zero value with the non-zero value.

18. A system as recited in claim 13, wherein the means for caching is configured to:

receive from the means for processing, an instruction to write a non-zero value;

determine a value that is to be replaced by the non-zero value; and

when the value to be replaced is a zero value in the means for caching zero data;

delete from the means for caching zero data, a cache line containing the zero value to be replaced;

write to the means for caching non-zero data, the cache line containing the zero value to be replaced; and

execute the write instruction to replace the zero value with the non-zero value.

19. A system as recited in claim 13, wherein the means for caching is configured to:

receive from the means for processing, an instruction to write a zero value;

determine a value that is to be replaced by the zero value; and

when the value to be replaced is a non-zero value in the means for caching non-zero data, execute the write instruction against the means for caching non-zero data to replace the non-zero value with the zero value.

20. A system as recited in claim 19, wherein when the value to be replaced is a non-zero value in the means for caching non-zero data, the means for caching is further configured to:

examine, in the means for caching non-zero data, a cache line that includes the zero value; and

when the cache line that includes the zero value includes other zero values and does not include a non-zero value;

write to the means for caching zero data, cache tags corresponding to the cache line containing the zero value; and

delete from the means for caching non-zero data, the cache line containing the zero value.