ZERO CACHE MEMORY SYSTEM EXTENSION
First Claim
Patent Images
1. A device comprising:
- a processor;
a memory communicatively coupled to the processor; and
a cache system communicatively coupled to the processor and the memory, wherein the cache system includes;
a data cache configured to store cache tags and data bytes associated with cache lines that include at least one non-zero value; and
a zero cache configured to store cache tags associated with zero cache lines.
1 Assignment
0 Petitions
Accused Products
Abstract
A zero cache memory system extension includes a zero cache to store cache tags associated with zero cache lines, while a corresponding data cache stores cache tags and data bytes associated with non-zero cache lines. As non-zero data is written to the cache, cache lines may be moved from the zero cache to the data cache. Similarly, as zero data is written to the cache, cache lines may be moved from the data cache to the zero cache.
-
Citations
20 Claims
-
1. A device comprising:
-
a processor; a memory communicatively coupled to the processor; and a cache system communicatively coupled to the processor and the memory, wherein the cache system includes; a data cache configured to store cache tags and data bytes associated with cache lines that include at least one non-zero value; and a zero cache configured to store cache tags associated with zero cache lines. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
-
-
9. A method comprising:
-
receiving from a processor, a read request; sending the read request to a data cache that stores cache lines that include non-zero data; sending the read request to a zero cache that stores zero cache lines; and in an event that the read request is satisfied by zero data in the zero cache, returning to the processor, an indication of a zero cache hit from the zero cache. - View Dependent Claims (10, 11, 12)
-
-
13. A system comprising:
-
means for processing; and means for caching, wherein the means for caching includes; means for caching non-zero data, the means for caching non-zero data communicatively coupled to the processor; and means for caching zero data, the means for caching zero data communicatively coupled to the processor. - View Dependent Claims (14, 15, 16, 17, 18, 19, 20)
-
Specification