SYSTEM COMPRISING A MASTER DEVICE AND A SLAVE DEVICE HAVING MULTIPLE INTEGRATED CIRCUIT DIE, WIRELESS COMMUNICATION UNIT AND METHOD THEREFOR

• US 20170192918A1
• Filed: 06/09/2016
• Published: 07/06/2017
• Est. Priority Date: 12/30/2015
• Status: Active Grant

• Current Assignee: MediaTek Singapore Pte. Ltd. (MediaTek, Inc.)
• Original Assignee: MediaTek Singapore Pte. Ltd. (MediaTek, Inc.)
• Inventors: Ivory, David Stephen, Tenbroek, Bernard Mark
• Granted Patent: US 10,042,798 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G06F 13/4291 using a clocked protocol

Abstract

A system is described that comprises: a master device and a slave device. The slave device comprises: a first die comprising an interface comprising a decoder configured to support a MIPI™ RFFE slave protocol; at least one second die comprising a simplified address decoder, operably coupled to the first die; and a shared control bus that is configured to support at least a clock signal and a data signal shared between the master device and the at least one second die on the slave device. The interface of the first die is configured to generate at least one circuit enable signal, routed to the at least one second die. The simplified address decoder is configured to process the clock signal and the data signal in response to the at least one circuit enable signal. In this manner, by partitioning the protocol handling to a protocol decoder in a first die, and one or more second die that support a simplified address decoder, the first die is able to individually select the die to receive a data frame by generating and routing the enable signal.

Claims

1. A system comprising:

a master device;

a slave device having;

a first die comprising an interface having a slave decoder configured to support a MIPI™

radio frequency front end, RFFE, slave protocol; and

at least one second die, comprising a simplified address decoder, operably coupled to the first die; and

a shared control bus configured to support at least a clock signal and a data signal shared between the master device, first die and the at least one second die on the slave device;

wherein the interface of the first die is configured to generate at least one circuit enable signal routed to the at least one second die and the simplified address decoder of the at least one second die is configured to process the clock signal and the data signal in response to the at least one circuit enable signal.

2. The system of claim 1 wherein the at least one second die is enabled to decode the data signal using the processed clock signal in response to the at least one circuit enable signal.

3. The system of claim 1 wherein the slave decoder is implemented on only the first die and configured to decode a first part of an input frame of the data signal comprising a command frame having at least one of:

a synchronisation field, a slave address field, and at least one command.

4. The system of claim 3 wherein the slave decoder is configured to identify whether the at least one second die is to decode a second part of the input frame based on the decoded first part, and generates the at least one circuit enable signal in response thereto.

5. The system of claim 4 wherein the second part of the input frame of the data signal comprises an address field and a data field to be decoded by the at least one second die.

6. The system of claim 1 wherein the first die comprises a first logic circuit coupled to the MIPI™

RFFE interface and configured to receive the clock signal and data signal from the shared bus and provide a gated version of the clock signal and data signal to the at least one second die.

7. The system of claim 1 further comprising multiple second die, each of the multiple second die comprising at least one storage element coupled to a respective simplified address decoder.

8. The system of claim 7 wherein the same enable signal is applied across multiple second die.

9. A method of operating a system comprising a master device and at least one slave device wherein the at least one slave device comprises a first die comprising a decoder configured to support a MIPI™

RFFE slave protocol and at least one second die comprising a simplified address decoder and operably coupled to the first die, the method comprising;

supporting at least a clock signal and a data signal between the master device and the at least one second die on the slave device via a shared control bus;

processing the data signal at the slave decoder on the first die to determine whether the at least one second die is to decode the data signal;

generating, at the first die, a circuit enable signal;

routing the circuit enable signal to the at least one second die;

processing the clock signal and the data signal by the simplified address decoder in response to the circuit enable signal.

10. The method of claim 9 further comprising:

decoding a first part of an input frame of the data signal by the slave decoder;

identifying whether the at least one second die is to decode a second part of the input frame based on the decoded first part; and

generating the at least one circuit enable signal in response thereto.

11. The method of claim 10 further comprising enabling the at least one second die to decode the data signal in response to the at least one circuit enable signal.

12. The method of claim 10 wherein the second part of the input frame of the data signal comprises an address field and a data field to be decoded by the at least one second die.

13. A wireless communication unit comprising:

a master device;

a slave device, comprising;

a first die comprising an interface having a slave decoder configured to support a MIPI™

radio frequency front end, RFFE, slave protocol;

at least one second die, comprising a simplified address decoder, operably coupled to the first die; and

a shared control bus configured to support at least a clock signal and a data signal shared between the master device, first die and the at least one second die on the slave device;

wherein the interface of the first die is configured to generate at least one circuit enable signal routed to the at least one second die and the simplified address decoder of the at least one second die is configured to process the clock signal and the data signal in response to the at least one circuit enable signal.

14. The wireless communication unit of claim 13 wherein the at least one second die is enabled to decode the data signal using the processed clock signal in response to the at least one circuit enable signal.

15. The wireless communication unit of claim 13 wherein the slave decoder is implemented on only the first die and configured to decode a first part of an input frame of the data signal comprising a command frame having at least one of:

a synchronisation field, a slave address field, and at least one command.

16. The wireless communication unit of claim 15 wherein the slave decoder is configured to identify whether the at least one second die is to decode a second part of the input frame based on the decoded first part, and generates the at least one circuit enable signal in response thereto.

17. The wireless communication unit of claim 16 wherein the second part of the input frame of the data signal comprises an address field and a data field to be decoded by the at least one second die.

18. The wireless communication unit of claim 13 wherein the first die comprises a first logic circuit coupled to the MIPI™

RFFE interface and configured to receive the clock signal and data signal from the shared bus and provide a gated version of the clock signal and data signal to the at least one second die.

19. The wireless communication unit of claim 13 further comprising multiple second die, each of the multiple second die comprising at least one storage element coupled to a respective simplified address decoder.

20. The wireless communication unit of claim 19 wherein the same enable signal is applied across multiple second die.