SHIFT CIRCUIT, SHIFT REGISTER, AND DISPLAY DEVICE
First Claim
1. A shift circuit of a shift register including a plurality of shift circuits that are cascade-connected, the shift circuit comprising:
- an input circuit which includes an input terminal to which an output signal of a shift circuit in a previous stage is supplied as an input signal, a reset terminal to which an output signal of a shift circuit in a next stage is supplied as a reset signal, and a first node, and is configured to set a potential of the first node as a potential of the input signal, as the input signal is input;
an inverting circuit including a second node and a reference voltage terminal, wherein the second node is configured to have a potential that is reverse to the potential of the first node obtained by reversing the potential of the first node;
an output circuit which includes a first clock terminal to which a first clock signal is supplied, and an output terminal which outputs the output signal, and is configured to output a potential of the output signal as a potential according to the first clock signal to the output terminal depending on the potential of the first node and the potential of the second node; and
a hold circuit configured to maintain the potential of the second node as a high level potential when the potential of the first node is not the potential of the input signal.
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Accused Products
Abstract
A shift resistor includes a first state and a second state and includes a plurality of shift circuits that are cascade-connected. Each shift circuit includes an output terminal which outputs state signal indicating the first or second states; an output control transistor T13 in which a clock signal is applied to second electrode; a charge means CQ connected between a first electrode and a first node Q of the output control transistor; a set transistor T11 which activates the first node based on a state signal output from shift circuit BCk−1 in a previous stage of the plurality of shift circuits and charges the charge means; and a reset transistor T15 which deactivates the first node based on a state signal output from shift circuit BCk+1 in a next stage of the plurality of shift circuits.
28 Citations
12 Claims
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1. A shift circuit of a shift register including a plurality of shift circuits that are cascade-connected, the shift circuit comprising:
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an input circuit which includes an input terminal to which an output signal of a shift circuit in a previous stage is supplied as an input signal, a reset terminal to which an output signal of a shift circuit in a next stage is supplied as a reset signal, and a first node, and is configured to set a potential of the first node as a potential of the input signal, as the input signal is input; an inverting circuit including a second node and a reference voltage terminal, wherein the second node is configured to have a potential that is reverse to the potential of the first node obtained by reversing the potential of the first node; an output circuit which includes a first clock terminal to which a first clock signal is supplied, and an output terminal which outputs the output signal, and is configured to output a potential of the output signal as a potential according to the first clock signal to the output terminal depending on the potential of the first node and the potential of the second node; and a hold circuit configured to maintain the potential of the second node as a high level potential when the potential of the first node is not the potential of the input signal. - View Dependent Claims (2, 3, 4, 5, 10, 11, 12)
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6. A shift circuit of a shift register which has a first state and a second state and includes a plurality of shift circuits that are cascade-connected, the shift circuit comprising:
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an output terminal configured to output a state signal indicating any one of the first state and the second state; an output control transistor in which a clock signal is applied to a second electrode, and a third electrode is connected to the output terminal; a charge means connected between a first electrode and a first node of the output control transistor; a set transistor configured to activate the first node based on a state signal output from a shift circuit in a previous stage of the plurality of shift circuits, and charge the charge means; and a reset transistor configured to deactivate the first node based on a state signal output from a shift circuit in a next stage of the plurality of shift circuits. - View Dependent Claims (7, 8, 9)
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Specification