PIXEL CIRCUIT, DISPLAY SUBSTRATE, DISPLAY DEVICE, AND METHOD FOR DRIVING DISPLAY SUBSTRATE

• US 20170193901A1
• Filed: 08/10/2016
• Published: 07/06/2017
• Est. Priority Date: 01/06/2016
• Status: Active Grant

• Current Assignee: BOE Technology Group Co., Ltd., Ordos Yuansheng Optoelectronics Co., Ltd. (BOE Technology Group Co., Ltd.)
• Original Assignee: BOE Technology Group Co., Ltd., Ordos Yuansheng Optoelectronics Co., Ltd. (BOE Technology Group Co., Ltd.)
• Inventors: WANG, Qiang, LIU, Libin
• Granted Patent: US 10,204,974 B2
• Time in Patent Office: Days
• CPC Class Codes: G09G 2300/0814 used for selection purposes, e.g. logical AND for partial update
• CPC Class Codes: G09G 2300/0819 used for counteracting undesired variations, e.g. feedback or autozeroing
• CPC Class Codes: G09G 2300/0823 used to establish symmetry in driving, e.g. with polarity inversion
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0861 with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
• CPC Class Codes: G09G 2310/0245 Clearing or presetting the whole screen independently of waveforms, e.g. on power-on G09G2310/063 takes precedence
• CPC Class Codes: G09G 2310/08 Details of timing specific for flat panels, other than clock recovery
• CPC Class Codes: G09G 2320/043 Preventing or counteracting the effects of ageing
• CPC Class Codes: G09G 2330/12 Test circuits or failure detection circuits included in a display system, as permanent part thereof
• CPC Class Codes: G09G 3/3233 with pixel circuitry controlling the current through the light-emitting element
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals

Abstract

The present disclosure relates to a pixel circuit, a display substrate, a display device, and a method for driving the display substrate. The pixel circuit includes an offset control unit, which is connected between a reset control terminal and a first end of an electroluminescent unit and is configured to be turned on in a case that a reset control signal is applied to the reset control terminal, and to set a voltage of the first end of the electroluminescent unit to be a voltage of the reset control signal.

Claims

1. A pixel circuit, comprising:

an electroluminescent unit, a display driving unit, an offset control unit, a reset control terminal and an initial voltage input terminal, wherein

the display driving unit is connected to the reset control terminal, the initial voltage input terminal, a first node, and a first end of the electroluminescent unit, and configured to generate a current having a corresponding amplitude according to a voltage at the first node, input the current to the first end of the electroluminescent unit, and set a voltage at the first node to be an initial voltage inputted at the initial voltage input terminal in response to a reset control signal inputted at the reset control terminal; and

the offset control unit is connected to the reset control terminal and the first end of the electroluminescent unit, and configured to be turned on in the case that the reset control signal is inputted at the reset control terminal, so as to set the voltage at the first end of the electroluminescent unit to be a voltage of the reset control signal.

2. The pixel circuit according to claim 1, wherein the offset control unit is configured to be turned on in the case that the reset control terminal is at a low voltage level, and the current generated by the display driving unit is a positive current.

3. The pixel circuit according to claim 2, wherein the offset control unit comprises a first transistor of a P-type, one of a source electrode and a drain electrode of the first transistor is connected to the first end of the electroluminescent unit, a gate electrode and the other one of the source electrode and the drain electrode of the first transistor are connected to the reset control terminal.

4. The pixel circuit according to claim 1, further comprising a light-emitting control terminal, wherein the display driving unit is further connected to the light-emitting control terminal, and configured to generate the current having the corresponding amplitude according to the voltage at the first node and input the current to the first end of the electroluminescent unit in the case that a light-emitting control signal is inputted to the light-emitting control terminal.

5. The pixel circuit according to claim 4, further comprising:

a data voltage input terminal, an operation voltage input terminal, a direct-current low voltage input terminal, and a writing and compensating control terminal;

the display driving unit comprises a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seven transistor which are all of the P-type, and comprises a capacitor;

a gate electrode of the second transistor is connected to the writing and compensating control terminal, one of a source electrode and a drain electrode of the second transistor is connected to the first node, and the other one of the source electrode and the drain electrode of the second transistor is connected to a third node;

a gate electrode of the third transistor is connected to the first node, one of a source electrode and a drain electrode of the third transistor is connected to a second node, and the other one of the source electrode and the drain electrode of the third transistor is connected to the third node;

a gate electrode of the fourth transistor is connected to the writing and compensating control terminal, one of a source electrode and a drain electrode of the fourth transistor is connected to the data voltage input terminal, and the other one of the source electrode and the drain electrode of the fourth transistor is connected to the second node;

both a gate electrode of the fifth transistor and a gate electrode of the sixth transistor are connected to the light-emitting control terminal, one of a source electrode and a drain electrode of the fifth transistor is connected to the operation voltage input terminal, and the other one of the source electrode and the drain electrode of the fifth transistor is connected to the second node, one of a source electrode and a drain electrode of the sixth transistor is connected to the first end of the electroluminescent unit, and the other one of the source electrode and the drain electrode of the sixth transistor is connected to the third node;

a gate electrode of the seventh transistor is connected to the reset control terminal, one of a source electrode and a drain electrode of the seventh transistor is connected to the initial voltage input terminal, and the other one of the source electrode and the drain electrode of the seventh transistor is connected to the first node;

one end of the capacitor is connected to the first node, and the other end of the capacitor is connected to the operation voltage input terminal; and

the light-emitting control signal is of a low voltage level.

6. A display substrate, comprising:

a base; and

a plurality of pixel circuits arranged on the base, wherein each of the plurality of pixel circuits is the pixel circuit according to claim 1.

7. A display substrate, comprising:

a base; and

a plurality of pixel circuits arranged on the base, wherein each of the plurality of pixel circuits is the pixel circuit according to claim 4, and the display substrate further comprises a first test wire and a second test wire, the first test wire is connected to the reset control terminals of the pixel circuits in each row, and the second test wire is connected to the light-emitting control terminals of the pixel circuits in each row.

8. The display substrate according to claim 7, wherein

each of the pixel circuits further comprises:

a data voltage input terminal, an operation voltage input terminal, a direct-current low voltage input terminal, and a writing and compensating control terminal;

the display driving unit comprises a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seven transistor which are all of the P-type, and comprises a capacitor;

a gate electrode of the second transistor is connected to the writing and compensating control terminal, one of a source electrode and a drain electrode of the second transistor is connected to the first node, and the other one of the source electrode and the drain electrode of the second transistor is connected to a third node;

a gate electrode of the third transistor is connected to the first node, one of a source electrode and a drain electrode of the third transistor is connected to a second node, and the other one of the source electrode and the drain electrode of the third transistor is connected to the third node;

a gate electrode of the fourth transistor is connected to the writing and compensating control terminal, one of a source electrode and a drain electrode of the fourth transistor is connected to the data voltage input terminal, and the other one of the source electrode and the drain electrode of the fourth transistor is connected to the second node;

both a gate electrode of the fifth transistor and a gate electrode of the sixth transistor are connected to the light-emitting control terminal, one of a source electrode and a drain electrode of the fifth transistor is connected to the operation voltage input terminal, and the other one of the source electrode and the drain electrode of the fifth transistor is connected to the second node, one of a source electrode and a drain electrode of the sixth transistor is connected to the first end of the electroluminescent unit, and the other one of the source electrode and the drain electrode of the sixth transistor is connected to the third node;

a gate electrode of the seventh transistor is connected to the reset control terminal, one of a source electrode and a drain electrode of the seventh transistor is connected to the initial voltage input terminal, and the other one of the source electrode and the drain electrode of the seventh transistor is connected to the first node;

one end of the capacitor is connected to the first node, and the other end of the capacitor is connected to the operation voltage input terminal; and

the light-emitting control signal is of a low voltage level.

9. The display substrate according to claim 7, further comprising a first scan driving circuit, a second scan driving circuit, a first test wire, a second test wire, a test switch array, and a plurality of test control wires configured for controlling the test switch array, wherein

the first scan driving circuit is configured to progressively output a reset control signal to the reset control terminals of the pixel circuits row by row, and the second scan driving circuit is configured to progressively output the light-emitting control signals to the light-emitting control terminals of the pixel circuits row by row;

the test switch array is connected to the first test wire, the second test wire and the plurality of test control wires, and configured to, at a display stage, in response to display control signals applied to the plurality of test control wires, disconnect the reset control terminal of each of the pixel circuits from the first test wire, disconnect the light-emitting control terminal of each of the pixel circuits from the second test wire, and connect the reset control terminal of each of the pixel circuits to the first scan driving circuit, and to, at a test stage, in response to a test control signal applied to the plurality of test control wires, connect the reset control terminal of each of the pixel circuits to the first test wire, connect the light-emitting control terminal of each of the pixel circuits to the second test wire, and disconnect the reset control terminal of each of the pixel circuits from the first scan driving circuit.

10. The display substrate according to claim 9, wherein

each of the plurality of the pixel circuits further comprises:

a data voltage input terminal, an operation voltage input terminal, a direct-current low voltage input terminal, and a writing and compensating control terminal;

the display driving unit comprises a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seven transistor which are all of the P-type, and comprises a capacitor;

a gate electrode of the second transistor is connected to the writing and compensating control terminal, one of a source electrode and a drain electrode of the second transistor is connected to the first node, and the other one of the source electrode and the drain electrode of the second transistor is connected to a third node;

a gate electrode of the third transistor is connected to the first node, one of a source electrode and a drain electrode of the third transistor is connected to a second node, and the other one of the source electrode and the drain electrode of the third transistor is connected to the third node;

a gate electrode of the fourth transistor is connected to the writing and compensating control terminal, one of a source electrode and a drain electrode of the fourth transistor is connected to the data voltage input terminal, and the other one of the source electrode and the drain electrode of the fourth transistor is connected to the second node;

both a gate electrode of the fifth transistor and a gate electrode of the sixth transistor are connected to the light-emitting control terminal, one of a source electrode and a drain electrode of the fifth transistor is connected to the operation voltage input terminal, and the other one of the source electrode and the drain electrode of the fifth transistor is connected to the second node, one of a source electrode and a drain electrode of the sixth transistor is connected to the first end of the electroluminescent unit, and the other one of the source electrode and the drain electrode of the sixth transistor is connected to the third node;

a gate electrode of the seventh transistor is connected to the reset control terminal, one of a source electrode and a drain electrode of the seventh transistor is connected to the initial voltage input terminal, and the other one of the source electrode and the drain electrode of the seventh transistor is connected to the first node;

one end of the capacitor is connected to the first node, and the other end of the capacitor is connected to the operation voltage input terminal; and

the light-emitting control signal is of a low voltage level.

11. The display substrate according to claim 9, wherein the test switch array comprises a plurality of first test switches, a plurality of second test switches, and a plurality of third test switches;

the pixel circuits in each row correspond to one of the plurality of the first test switches, one of the plurality of the second test switches, and one of the plurality of the third test switches; and

the one of the plurality of the first test switches is connected between the light-emitting control terminals of the pixel circuits in the row and the second test wire, the one of the plurality of the second test switches is connected between the reset control terminals of the pixel circuits in the row and the first scan driving circuit, and the one of the plurality of the third test switches is connected between the reset control terminals of the pixel circuits in the row and the first test wire.

12. The display substrate according to claim 10, wherein the test switch array comprises a plurality of first test switches, a plurality of second test switches, and a plurality of third test switches;

the pixel circuits in each row correspond to one of the plurality of the first test switches, one of the plurality of the second test switches, and one of the plurality of the third test switches; and

the one of the plurality of the first test switches is connected between the light-emitting control terminals of the pixel circuits in the row and the second test wire, the one of the plurality of the second test switches is connected between the reset control terminals of the pixel circuits in the row and the first scan driving circuit, and the one of the plurality of the third test switches is connected between the reset control terminals of the pixel circuits in the row and the first test wire.

13. A method for driving the display substrate according to claim 6, comprising:

at a reverse offset stage included in a display stage, progressively outputting a reset control signal to the reset control terminals of the pixel circuits row by row, wherein an absolute value of a voltage of the reset control signal is greater than an absolute value of the initial voltage applied at the initial voltage input terminal.

14. A method for driving the display substrate according to claim 7, comprising:

at a reverse offset stage included in a display stage, progressively outputting a reset control signal to the reset control terminals of the pixel circuits row by row, wherein an absolute value of a voltage of the reset control signal is greater than an absolute value of the initial voltage applied at the initial voltage input terminal; and

at a test stage, applying a light emission driving voltage to the first test wire, and applying a voltage having a level reverse to a level of the light-emitting control signal to the second test wire.

15. A method for driving the display substrate according to claim 9, comprising:

at a reverse offset stage included in a display stage, progressively outputting a reset control signal to the reset control terminals of the pixel circuits row by row, wherein an absolute value of a voltage of the reset control signal is greater than an absolute value of the initial voltage applied at the initial voltage input terminal;

at the display stage, applying the display control signals to the plurality of test control wires;

at the test stage, applying the test control signals to the plurality of test control wires, applying a light emission driving voltage to the first test wire, and applying a voltage having a level reverse to a level of the light-emitting control signal to the second test wire, wherein the light emission driving voltage is adapted to turn on offset control units and enable the pixel circuits to emit light.

16. The method according to claim 15, wherein the test switch array comprises a plurality of first test switches, a plurality of second test switches, and a plurality of third test switches;

the pixel circuits in each row correspond to one of the plurality of the first test switches, one of the plurality of the second test switches, and one of the plurality of the third test switches; and

the one of the plurality of the first test switches is connected between the light-emitting control terminals of the pixel circuits in the row and the second test wire, the one of the plurality of the second test switches is connected between the reset control terminals of the pixel circuits in the row and the first scan driving circuit, and the one of the plurality of the third test switches is connected between the reset control terminals of the pixel circuits in the row and the first test wire.

17. A display device, comprising the display substrate according to claim 6.

18. A display device, comprising the display substrate according to claim 7.

19. The display device according to claim 18, wherein each of the plurality of pixel circuits further comprises:

a data voltage input terminal, an operation voltage input terminal, a direct-current low voltage input terminal, and a writing and compensating control terminal;

the display driving unit comprises a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, and a seven transistor which are all of the P-type, and comprises a capacitor;

a gate electrode of the second transistor is connected to the writing and compensating control terminal, one of a source electrode and a drain electrode of the second transistor is connected to the first node, and the other one of the source electrode and the drain electrode of the second transistor is connected to a third node;

a gate electrode of the third transistor is connected to the first node, one of a source electrode and a drain electrode of the third transistor is connected to a second node, and the other one of the source electrode and the drain electrode of the third transistor is connected to the third node;

a gate electrode of the fourth transistor is connected to the writing and compensating control terminal, one of a source electrode and a drain electrode of the fourth transistor is connected to the data voltage input terminal, and the other one of the source electrode and the drain electrode of the fourth transistor is connected to the second node;

both a gate electrode of the fifth transistor and a gate electrode of the sixth transistor are connected to the light-emitting control terminal, one of a source electrode and a drain electrode of the fifth transistor is connected to the operation voltage input terminal, and the other one of the source electrode and the drain electrode of the fifth transistor is connected to the second node, one of a source electrode and a drain electrode of the sixth transistor is connected to the first end of the electroluminescent unit, and the other one of the source electrode and the drain electrode of the sixth transistor is connected to the third node;

a gate electrode of the seventh transistor is connected to the reset control terminal, one of a source electrode and a drain electrode of the seventh transistor is connected to the initial voltage input terminal, and the other one of the source electrode and the drain electrode of the seventh transistor is connected to the first node;

one end of the capacitor is connected to the first node, and the other end of the capacitor is connected to the operation voltage input terminal; and

the light-emitting control signal is of a low voltage level.

20. A display device comprising the display substrate according to claim 8.