DISPLAY DRIVING CIRCUIT, METHOD FOR CONTROLLING THE DISPLAY DRIVING CIRCUIT, AND DISPLAY DEVICE

• US 20170193931A1
• Filed: 07/28/2016
• Published: 07/06/2017
• Est. Priority Date: 01/04/2016
• Status: Active Grant

• Current Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Original Assignee: Beijing BOE Optoelectronics Technology Co Ltd. (BOE Technology Group Co., Ltd.), BOE Technology Group Co., Ltd.
• Inventors: HAN, Peng, LI, Yafei, GAO, Bo, ZHANG, Hao, SHI, Lingyun, WANG, Xiurong
• Granted Patent: US 10,223,995 B2
• Time in Patent Office: Days
• CPC Class Codes: G09G 2300/023 Display panel composed of stacked panels
• CPC Class Codes: G09G 2310/0286 Details of a shift registers arranged for use in a driving circuit
• CPC Class Codes: G09G 3/3266 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3275 Details of drivers for data electrodes
• CPC Class Codes: G09G 3/3611 Control of matrices with row and column drivers
• CPC Class Codes: G09G 3/3674 Details of drivers for scan electrodes
• CPC Class Codes: G09G 3/3685 Details of drivers for data electrodes

Abstract

A display driving circuit, a method for controlling the display driving circuit, and a display device are provided. The display driving circuit is for driving pixel cells located on a liquid crystal display panel and sub-pixels located on an OLED display panel, one pixel cell corresponding to at least one sub-pixel. The display driving circuit comprises a shift register unit which outputs a signal inputted from a source signal terminal to a signal output terminal under the control of a pulse signal terminal. One pixel cell and at least one sub-pixel corresponding to the pixel cell are connected to the same signal output terminal. The display driving circuit is for driving a display panel to display, and is capable of solving the problems of a complex product structure and cost rising due to the separate arrangement of driver ICs for driving the OLED display panel and the liquid crystal display panel.

Claims

1. A display driving circuit for driving pixel cells located on a liquid crystal display panel and sub-pixels located on an OLED display panel, one of the pixel cells corresponding to at least one of the sub-pixels, the display driving circuit comprising:

a shift register unit connected respectively to a source signal terminal, a pulse signal terminal, and at least one signal output terminal, and configured to output a signal inputted from the source signal terminal to the signal output terminal under control of the pulse signal terminal;

wherein one pixel cell and at least one sub-pixel corresponding to the one pixel cell are connected to the same signal output terminal.

2. The display driving circuit as claimed in claim 1, wherein the at least one sub-pixel corresponding to one of the pixel cells includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, the at least one signal output terminal includes a first signal output terminal, a second signal output terminal, and a third signal output terminal;

the first signal output terminal is connected to the pixel cell and the first sub-pixel;

the second signal output terminal is connected to the pixel cell and the second sub-pixel;

the third signal output terminal is connected to the pixel cell and the third sub-pixel; and

light rays that transmit through the first sub-pixel, the second sub-pixel, and the third sub-pixel respectively constitute light rays of three primary colors.

3. The display driving circuit as claimed in claim 1, wherein it further comprises a gate driver and a source driver;

the gate driver is connected to the pixel cell via a first gate line, and configured to control tuning-on of the pixel cell via the first gate line;

the gate driver is connected to the sub-pixel via a second gate line, and configured to control tuning-on of the sub-pixel via the second control gate line; and

the source driver is connected to the source signal terminal, and configured to output a data signal to the source signal terminal.

4. The display driving circuit as claimed in claim 1, wherein it further comprises a pulse signal generator connected to the pulse signal terminal and configured to input a pulse signal to the pulse signal terminal.

5. The display driving circuit as claimed in claim 3, wherein the first gate line and the second gate line are connected to each other.

6. A display device, comprising a liquid crystal display panel and an OLED display panel disposed opposite to each other, and further comprising the display driving circuit according to claim 1.

7. A method for controlling the display driving circuit according to claim 1, comprising:

outputting, by the shift register unit, a signal from the source signal terminal to the signal output terminal under control of the pulse signal terminal; and

charging, by the signal output terminal, pixel cells and sub-pixels that are connected to the same signal output terminal.

8. The method for controlling the display driving circuit as claimed in claim 7, wherein in a case where the at least one sub-pixel corresponding to one of the pixel cells includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, the at least one signal output terminal includes a first signal output terminal, a second signal output terminal, and a third signal output terminal, the method comprises:

inputting a first pulse signal from the pulse signal terminal, outputting a signal from the source signal terminal to the first signal output terminal and charging the pixel cell and the first sub-pixel via the first signal output terminal by the shift register unit;

inputting a second pulse signal from the pulse signal terminal, outputting a signal from the source signal terminal to the second signal output terminal and charging the pixel cell and the second sub-pixel via the second signal output terminal by the shift register unit; and

inputting a third pulse signal from the pulse signal terminal, outputting a signal from the source signal terminal to the third signal output terminal and charging the pixel cell and the third sub-pixel via the third signal output terminal by the shift register unit.

9. The method for controlling the display driving circuit as claimed in claim 7, wherein prior to outputting, by the shift register unit, a signal from the source signal terminal to the signal output terminal under the control of the pulse signal terminal, the method comprises:

controlling, by the gate driver, tuning-on of the pixel cell via the first gate line;

controlling, by the gate driver, tuning-on of the sub-pixel corresponding to the pixel cell via the second gate line; and

outputting, by the source driver, a data signal to the source signal terminal.

10. The method for controlling the display driving circuit as claimed in claim 7, wherein prior to outputting, by the shift register unit, a signal from the source signal terminal to the signal output terminal under the control of the pulse signal terminal, the method comprises:

inputting, by a pulse signal generator, a pulse signal to the pulse signal terminal.

11. The display device as claimed in claim 6, wherein the at least one sub-pixel corresponding to one of the pixel cells includes a first sub-pixel, a second sub-pixel and a third sub-pixel, the at least one signal output terminal includes a first signal output terminal, a second signal output terminal, and a third signal output terminal;

the first signal output terminal is connected to the pixel cell and the first sub-pixel;

the second signal output terminal is connected to the pixel cell and the second sub-pixel;

the third signal output terminal is connected to the pixel cell and the third sub-pixel; and

light rays that transmit through the first sub-pixel, the second sub-pixel, and the third sub-pixel respectively constitute light rays of three primary colors.

12. The display device as claimed in claim 6, wherein it further comprises a gate driver and a source driver;

the gate driver is connected to the pixel cell via a first gate line, and configured to control tuning-on of the pixel cell via the first gate line;

the gate driver is connected to the sub-pixel via a second gate line, and configured to control tuning-on of the sub-pixel via the second control gate line; and

the source driver is connected to the source signal terminal, and configured to output a data signal to the source signal terminal.

13. The display device as claimed in claim 6, wherein it further comprises a pulse signal generator connected to the pulse signal terminal and configured to input a pulse signal to the pulse signal terminal.

14. The display device as claimed in claim 12, wherein the first gate line and the second gate line are connected to each other.

15. The method for controlling the display driving circuit as claimed in claim 7, wherein in the display driving circuit, the at least one sub-pixel corresponding to one of the pixel cells includes a first sub-pixel, a second sub-pixel, and a third sub-pixel, the at least one signal output terminal includes a first signal output terminal, a second signal output terminal, and a third signal output terminal;

the first signal output terminal is connected to the pixel cell and the first sub-pixel;

the second signal output terminal is connected to the pixel cell and the second sub-pixel;

the third signal output terminal is connected to the pixel cell and the third sub-pixel; and

light rays that transmit through the first sub-pixel, the second sub-pixel, and the third sub-pixel respectively constitute light rays of three primary colors.

16. The method for controlling the display driving circuit as claimed in claim 7, wherein the display driving circuit further comprises a gate driver and a source driver;

the gate driver is connected to the pixel cell via a first gate line, and configured to control tuning-on of the pixel cell via the first gate line;

the gate driver is connected to the sub-pixel via a second gate line, and configured to control tuning-on of the sub-pixel via the second control gate line; and

the source driver is connected to the source signal terminal, and configured to output a data signal to the source signal terminal.

17. The method for controlling the display driving circuit as claimed in claim 7, wherein the display driving circuit further comprises a pulse signal generator connected to the pulse signal terminal and configured to input a pulse signal to the pulse signal terminal.

18. The method for controlling the display driving circuit as claimed in claim 16, wherein in the display driving circuit, the first gate line and the second gate line are connected.