METHOD FOR SUPPRESSING GATE OXIDE TUNNEL CURRENT IN NON-VOLATILE MEMORY TO REDUCE DISTURBS

• US 20170194056A1
• Filed: 12/29/2016
• Published: 07/06/2017
• Est. Priority Date: 12/30/2015
• Status: Active Grant

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: HEINRICH-BARNA, Stephen K., DUNN, Clyde F., MEHTA, Aswin N., MACPEAK, John H.
• Granted Patent: US 10,535,409 B2
• Time in Patent Office: Days
• CPC Class Codes: G11C 16/0425 comprising cells containing a merged floating gate and select transistor
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written

Abstract

A disturb management technique for a non-volatile memory including first and second memory cells includes programming the first memory cell by applying a first voltage to a first word line coupled to the first memory cell and a second voltage to a terminal, such as a source terminal, shared by the first memory cell and the second memory cell. A non-zero third voltage having the same sign as the second voltage is applied to a second word line coupled to the second memory cell. The applied non-zero third voltage reduces a tunnel current across a gate oxide that insulates the second word line from a substrate of the second memory cell. This results in the second memory cell having a lower likelihood of being disturbed when programming the first memory cell.

Claims

1. A method of operating a memory device having a non-volatile memory array including first and second memory cells, the method comprising:

programming the first memory cell by applying a first voltage to a first word line coupled to the first memory cell and a second voltage to a first terminal that is shared by the first memory cell and the second memory cell; and

applying a third voltage to a second word line coupled to the second memory cell, wherein the third voltage is a non-zero voltage, wherein applying the third voltage reduces a tunnel current across a gate oxide insulating the second word line from a substrate of the second memory cell.

2. The method of claim 1, wherein the third voltage has the same sign as the second voltage.

3. The method of claim 1, wherein a voltage difference between the second word line and the shared first terminal when the non-zero voltage is applied to the second word line is reduced compared to when a zero voltage is applied to the second word line.

4. The method of claim 3, wherein reducing the voltage difference using the non-zero voltage reduces the strength of an electric field causing the tunnel current.

5. The method of claim 3, wherein the shared first terminal is a shared source terminal of the first and second memory cells.

6. The method of claim 5, wherein the non-zero voltage applied to the second word line is between approximately 0.1V and 0.5V, the first voltage applied to the first word line is between approximately 0.8V and 1.3V, and the second voltage applied to the shared source terminal is between approximately 4V and 5V.

7. The method of claim 5, wherein the first and second memory cells include split gate transistors having a substrate that includes the shared source terminal, a drain terminal formed in the substrate, a channel region formed in the substrate between the drain terminal and the shared source terminal, a select gate positioned over a first portion of the channel region, a floating gate positioned over a second portion of the channel region and located closer to the shared source terminal than the select gate, and a control gate positioned over the floating gate, and wherein the select gate of the first memory cell is coupled to the first word line and the select gate of the second memory cell is coupled to the second word line.

8. The method of claim 7, wherein the control gate of the first memory cell and the control gate of the second memory cell are controlled by a common driver circuit.

9. The method of claim 7, comprising an erase gate positioned over the shared source terminal, the erase gate being shared by the first and second memory cells.

10. The method of claim 1, wherein the first and second memory cells are adjacent memory cells coupled to the same bit line in the non-volatile memory array.

11. The method of claim 1, wherein the second memory cell is in an erased state during the programming of the first memory cell.

12. A memory device comprising:

a non-volatile memory array having a plurality of memory cells, the plurality of memory cells including a first memory cell coupled to a first word line and a second memory cell coupled to a second word line, the first and second memory cells being directly adjacent to each other and coupled to the same bit line;

word line driving circuitry that applies voltages to the first and second word lines; and

control circuitry that receives commands to retrieve data from or to store data to the non-volatile memory array;

wherein, when the control circuitry receives a command for programming the first memory cell, a first voltage is applied to a terminal shared by the first and second memory cells, and the word line driving circuitry applies a second voltage to the first word line and a third voltage to the second word line, the third voltage being a non-zero voltage that reduces a tunnel current across a gate oxide insulating the second word line from a substrate of the second memory cell.

13. The memory device of claim 12, comprising a source line driver, wherein the shared terminal is a source terminal and the first voltage is applied to the shared source terminal by the source line driver.

14. The memory device of claim 13, wherein a voltage difference between the second word line and the shared source terminal when the non-zero voltage is applied to the second word line is reduced compared to when a zero voltage is applied to the second word line.

15. The memory device of claim 13, wherein each of the first and second memory cells are split gate transistors, each including a substrate that includes the shared source terminal, a drain terminal formed in the substrate, a channel region defined between the drain terminal and the shared source terminal, a select gate positioned over a first portion of the channel region, a floating gate positioned over a second portion of the channel region and located closer to the source terminal than the select gate, and a control gate positioned over the floating gate;

wherein the select gate of the first memory cell is coupled to the first word line and the select gate of the second memory cell is coupled to the second word line.

16. The memory device of claim 15, wherein the control gate of the first memory cell and the control gate of the second memory cell are controlled by a common control gate driver circuit.

17. The memory device of claim 13, wherein the first voltage applied to the shared source terminal is between approximately 4V and 5V, the second voltage applied to the first word line is between approximately 0.8V and 1.3V, and the third voltage applied to the second word line is between approximately 0.1V and 0.5V.

18. The memory device of claim 12, wherein the third voltage is less than the second voltage.

19. The memory device of claim 12, wherein the third voltage is less than the first voltage.

20. The memory device of claim 12, wherein the gate oxide has a thickness of less than approximately 30 angstroms.

21. A memory device comprising:

a non-volatile memory array having a plurality of memory cells including a first memory cell coupled to a first word line and a second memory cell coupled to a second word line, the first and second word lines being adjacent to one another;

control circuitry that receives commands to retrieve data from or to store data to the non-volatile memory array;

driving circuitry that, when the control circuitry receives a command for programming the first memory cell, applies a first voltage to a first terminal of the first memory cell, a second voltage to the first word line, and a third voltage to the second word line, the third voltage being a non-zero voltage having the same sign as the first voltage.

22. The memory device of claim 21, wherein the first terminal of the first memory cell is a source terminal that is shared with the second memory cell, and wherein a voltage difference between the second word line and the shared source terminal when the third voltage is applied to the second word line is reduced compared to when a zero voltage is applied to the second word line.

23. The memory device of claim 22, wherein the third voltage is less than the first voltage.

24. The memory device of claim 22, wherein the third voltage is less than the second voltage.

25. The memory device of claim 21, wherein the first and second memory cells are directly adjacent to each other and coupled to a same bit line.