METHOD OF MAKING A SEMICONDUCTOR DEVICE FORMED BY THERMAL ANNEALING

• US 20170194148A1
• Filed: 12/30/2015
• Published: 07/06/2017
• Est. Priority Date: 12/30/2015
• Status: Active Grant

• Current Assignee: Infineon Technologies AG
• Original Assignee: Infineon Technologies AG
• Inventors: Voss, Stephan, Breymesser, Alexander
• Granted Patent: US 9,704,712 B1
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/02675 using laser beams
• CPC Class Codes: H01L 21/2252 using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
• CPC Class Codes: H01L 21/2255 the applied layer comprising oxides only, e.g. P2O5, PSG, H3BO3, doped oxides
• CPC Class Codes: H01L 21/2258 Diffusion into or out of AIIIBV compounds
• CPC Class Codes: H01L 21/26513 of electrically active species
• CPC Class Codes: H01L 21/268 using electromagnetic radiation, e.g. laser radiation
• CPC Class Codes: H01L 21/308 using masks H01L21/3063, H01L21/3065 take precedence
• CPC Class Codes: H01L 29/0684 characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
• CPC Class Codes: H01L 29/0834 Anode regions of thyristors or gated bipolar-mode devices, e.g. supplementary regions surrounding anode regions
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/34 the imperfections being on the surface
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/861 Diodes

Abstract

According to various embodiments, a method may include: structuring a semiconductor region to form a structured surface of the semiconductor region; disposing a dopant in the semiconductor region; and activating the dopant at least partially by irradiating the structured surface at least partially with electromagnetic radiation having at least one discrete wavelength to heat the semiconductor region at least partially.

Claims

1. A method comprising:

structuring a semiconductor region to form a structured surface of the semiconductor region;

disposing a dopant in the semiconductor region;

activating the dopant at least partially by irradiating the structured surface at least partially with electromagnetic radiation having at least one discrete wavelength to heat the semiconductor region at least partially; and

forming a doped region on at least one of over or in the semiconductor region at a side opposite the dopant, wherein the doped region comprises a doping type different to the dopant to form a power semiconductor circuit element comprising the dopant and the doped region.

2. The method of claim 1,

wherein the dopant is disposed in the semiconductor region at least one of before and after the structuring the semiconductor region.

3. The method of claim 1,

wherein the semiconductor region is heated substantially only through the structured surface.

4. The method of claim 1,

wherein the electromagnetic radiation comprises at least one of pulsed radiation and coherent radiation.

5. The method of claim 1,

wherein heating the semiconductor region comprises a thermal non-equilibrium heating process.

7. The method of claim 1,

wherein the semiconductor region is structured such that a first reflection characteristic of a first region of the structured surface is different from a second reflection characteristic of a second region of the structured surface.

8. The method of claim 1,

wherein the structured surface comprises at least one of:

a facetted structure, a pyramid structure, a trench structure, a needle structure, a hole structure, a porous structure, plurality of tapered protrusions.

9. The method of claim 1,

wherein the structuring the semiconductor region comprises forming random pyramids by anisotropically etching the semiconductor region.

10. The method of claim 1,

wherein structuring the semiconductor region comprises using a mask for adjusting a spatial distribution of a reflectance of the structured surface.

11. The method of claim 1,

wherein the structured surface is heated to a temperature less than an evaporation temperature of the structured surface during activating the dopant.

12. The method of claim 1,

wherein activating the dopant comprises at least partially recrystallizing the semiconductor region.

13. The method of claim 1,

wherein a roughness of the semiconductor region is increased during the structuring the semiconductor region;

and

wherein the roughness of the semiconductor region is reduced during the activating of the dopant.

14. The method of claim 1,

wherein irradiating the structured surface comprises using a laser source.

15. The method of claim 1, further comprising:

forming at least one collector contact pad in electrical contact to the structured surface.

16. The method of claim 1,

wherein structuring the semiconductor region comprises thinning the semiconductor region.

17. The method of claim 1,

wherein activating the dopant comprises forming a doped surface layer within the semiconductor region.

18. The method of claim 1,

wherein the structured surface is configured to provide multiple reflections of the electromagnetic radiation incident on the structured surface.

19. The method of claim 1,

wherein a reflectance of the structured surface is less than about 0.5 for electromagnetic radiation in the range from about 250 nm to about 350 nm and incident along a direction of a macroscopic surface normal of the structured surface.

6. (canceled)

20. A method comprising:

structuring a semiconductor region to form a structured surface of the semiconductor region at a first side of the semiconductor region;

disposing a dopant at least one of over or in the semiconductor region at the first side of the semiconductor region; and

activating the dopant at least partially by irradiating the structured surface at least partially with electromagnetic radiation to at least a portion of the semiconductor region at the first side of the semiconductor region; and

forming a doped region on at least one of over or in the semiconductor region at a second side of the semiconductor region opposite the first side, wherein the doped region comprises a doping type different to the dopant to form a power semiconductor circuit element comprising the dopant and the doped region.

21. The method of claim 20,

wherein the power semiconductor circuit element comprises at least one transistor structure.

22. The method of claim 20,

wherein the power semiconductor circuit element comprises a vertical structure.

23. The method of claim 20,

wherein structuring the semiconductor region comprises thinning the semiconductor region.

24. A semiconductor device, comprising:

a semiconductor region comprising a structured surface and an activated dopant;

wherein the activated dopant is disposed adjacent to the structured surface;

wherein the structured surface comprises at least one of a plurality of rounded protrusions, or a plurality of rounded recesses.