Recessed STI as the Gate Dielectric of HV Device

• US 20170194320A1
• Filed: 03/04/2016
• Published: 07/06/2017
• Est. Priority Date: 12/30/2015
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Thei, Kong-Beng, Fan, Fu-Jier, Chen, Yi-huan, Huo, Ker-Hsiao, Lin, Kau-Chu, Yeh, Li-Hsuan, Liu, Szu-Hsien, Chen, Yi-Sheng
• Granted Patent: US 10,916,542 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/823418 with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 21/823493 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/0692 Surface layout
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/1087 characterised by the contact structure of the substrate region, e.g. for controlling or preventing bipolar effect
• CPC Class Codes: H01L 29/42364 characterised by the insulating layer, e.g. thickness or uniformity H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
• CPC Class Codes: H01L 29/66621 using etching to form a recess at the gate location etching of semiconductor bodies H01L21/302

Abstract

A method includes forming an isolation region extending into a semiconductor substrate, etching a top portion of the isolation region to form a recess in the isolation region, and forming a gate stack extending into the recess and overlapping a lower portion of the isolation region. A source region and a drain region are formed on opposite sides of the gate stack. The gate stack, the source region, and the drain region are parts of a Metal-Oxide-Semiconductor (MOS) device.

Claims

1. A method comprising:

forming an isolation region extending into a semiconductor substrate;

etching a top portion of the isolation region to form a recess in the isolation region;

forming a gate stack extending into the recess and overlapping a lower portion of the isolation region; and

forming a source region and a drain region on opposite sides of the gate stack, wherein the gate stack, the source region, and the drain region are parts of a Metal-Oxide-Semiconductor (MOS) device.

2. The method of claim 1, wherein the MOS device is a High-Voltage (HV) MOS device, and the method further comprises:

implanting the semiconductor substrate to form an HV n-well region and an HV p-well region, wherein at least one of the HV n-well region and an HV p-well region comprises a portion underlying the isolation region.

3. The method of claim 1, wherein a middle portion of the top portion of the isolation region is etched, and after the etching, the top portion of the isolation region further comprises additional portions remaining on a side of the etched middle portion.

4. The method of claim 1, wherein the isolation region has a top surface substantially coplanar with a top surface of the semiconductor substrate.

5. The method of claim 1 comprising simultaneously forming the isolation region and an additional isolation region, wherein during the etching, the additional isolation region is not etched.

6. The method of claim 1 further comprising:

when the gate stack is formed, simultaneously forming an additional gate stack for an additional MOS device, wherein the additional gate stack is directly over an un-recessed portion of the semiconductor substrate; and

performing a planarization to level a top surface of the gate stack and the additional gate stack.

7. The method of claim 6 further comprising replacing the gate stack and the additional gate stack with a first replacement gate stack and a second replacement gate stack, respectively.

8. The method of claim 6, wherein a bottom surface of the gate stack is lower than a top surface of the semiconductor substrate, and a bottom surface of the additional gate stack is higher than a top surface of the semiconductor substrate.

9. A method comprising:

forming a first and a second Shallow Trench Isolation (STI) region extending from a top surface of a semiconductor substrate into the semiconductor substrate;

etching the first STI region to form a recess extending from a top surface of the first STI region into the first STI region, wherein the first STI region comprises a lower portion underlying the recess;

forming a first gate stack overlapping the lower portion of the first STI region;

forming a second gate stack over and contacting a top surface of the semiconductor substrate;

forming first source/drain regions on opposite sides of the first gate stack;

forming second source/drain regions on opposite sides of the second gate stack, wherein one of the second source/drain regions contacts a sidewall of the second STI region;

filling an Inter-Layer Dielectric (ILD) over the first source/drain regions and the second source/drain regions; and

performing a planarization to make a top surface of the first gate stack to be coplanar with a top surface of the second gate stack.

10. The method of claim 9, wherein the first gate stack acts as a stop layer for the planarization, and a top portion of the second gate stack is removed by the planarization.

11. The method of claim 9, wherein the first gate stack is a part of a high-voltage Metal-Oxide-Semiconductor (MOS) device, and the second gate stack is a part of a medium-voltage MOS device or a low-voltage MOS device.

12. The method of claim 11, wherein the lower portion of the first STI region acts as a portion of a gate dielectric of the HV MOS device.

13. The method of claim 9, wherein a portion of the first gate stack is lower than the top surface of the semiconductor substrate, and an entirety of the second gate stack is higher than a top surface of the semiconductor substrate.

14. The method of claim 9 further comprising replacing the first gate stack and the second gate stack with a first replacement gate and a second replacement gate, respectively.

15-20. -20. (canceled)

21. A method comprising:

forming a first high-voltage well region, a second high-voltage well region, and a third high-voltage well region extending from a top surface of a semiconductor substrate into the semiconductor substrate, wherein the second and the third high-voltage well regions are on opposite sides of the first high-voltage well region;

forming an isolation region extending from a top surface of the first high-voltage well region into the first high-voltage well region;

etching the isolation region, wherein the isolation region remaining after the isolation region is etched comprises a bottom portion, and two sidewall portions connected to opposite ends of the bottom portion;

forming a gate stack overlapping the bottom portion of the isolation region; and

forming a source region and a drain region in the second and the third high-voltage well regions, respectively.

22. The method of claim 21, wherein the etching the isolation region comprises:

forming a patterned photo resist covering the second and the third high-voltage well regions and the two sidewall portions of the isolation region, wherein the isolation region is etching using the patterned photo resist as an etching mask.

23. The method of claim 21, wherein the gate stack is horizontally spaced apart from the two sidewall portions of the isolation region.

24. The method of claim 23 further comprising forming gate spacers on opposite sidewalls of the gate stack, wherein the gate spacers are spaced apart from the two sidewall portions of the isolation region.

25. The method of claim 21, wherein the first high-voltage well region is of a first conductivity type opposite to a second conductivity type of the second and the third high-voltage well regions, and the isolation region further extends into the second and the third high-voltage well regions.

26. The method of claim 21, wherein the etching the isolation region results in a recess in the isolation region, and the method further comprises forming a contact etch stop layer over the source region and the drain region, wherein the contact etch stop layer extends into the recess.