NARROW BORDER TOUCH SCREEN

• US 20170199618A1
• Filed: 09/23/2014
• Published: 07/13/2017
• Est. Priority Date: 05/28/2014
• Status: Active Grant

• Current Assignee: Apple Inc.
• Original Assignee: Apple Inc.
• Inventors: CHANG, Shih-Chang, CHANG, Ting-Kuo, YU, Cheng-Ho, JAMSHIDI-ROUDBARI, Abbas
• Granted Patent: US 10,852,876 B2
• Time in Patent Office: Days
• CPC Class Codes: G06F 2203/04104 Multi-touch detection in digitiser, i.e. details about the simultaneous detection of a plurality of touching locations, e.g. multiple fingers or pen and finger
• CPC Class Codes: G06F 2203/04108 Touchless 2D- digitiser, i.e. digitiser detecting the X/Y position of the input means, finger or stylus, also when it does not touch, but is proximate to the digitiser's interaction surface without distance measurement in the Z direction
• CPC Class Codes: G06F 3/0412 Digitisers structurally integrated in a display
• CPC Class Codes: G06F 3/0416 Control or interface arrangements specially adapted for digitisers
• CPC Class Codes: G06F 3/04164 Connections between sensors and controllers, e.g. routing lines between electrodes and connection pads
• CPC Class Codes: G06F 3/04166 Details of scanning methods, e.g. sampling time, grouping of sub areas or time sharing with display driving Synchronisation with the driving of the display or the backlighting unit to avoid interferences generated internally G06F3/04184
• CPC Class Codes: G06F 3/044 by capacitive means
• CPC Class Codes: G06F 3/0443 using a single layer of sensing electrodes
• CPC Class Codes: G06F 3/0445 using two or more layers of sensing electrodes, e.g. using two layers of electrodes separated by a dielectric layer

Abstract

A touch screen is disclosed that includes conductive elements in a display area and connecting traces for routing the conductive elements to other locations. The connecting traces can be routed underneath or over existing opaque structures in the display area, instead of in border areas adjacent to the display area, to minimize the effect of the connecting traces on the display aperture ratio. The lengths and/or widths of these connecting traces as well as the number of parallel connecting traces used to connect to a particular element can be selected to balance the load on the drive and/or sense circuitry and on display pixels caused by the connecting traces.

Claims

1. A touch screen comprising:

a plurality of elements formed in a display area of the touch screen; and

a plurality of connecting traces coupled to the plurality of elements and routed in the display area;

wherein the plurality of connecting traces are configured to;

substantially balance a load created by the connecting traces, and

substantially not affect an aperture ratio of the touch screen.

2. The touch screen of claim 1, wherein one or more first connecting traces coupled to a first element are configured such that a total resistance of the one or more first connecting traces substantially matches a total resistance of one or more second connecting traces coupled to a second element.

3. The touch screen of claim 2, wherein a length of the one or more first connecting traces is selected such that the total resistance of the one or more first connecting traces substantially matches the total resistance of the one or more second connecting traces.

4. The touch screen of claim 2, wherein a width of the one or more first connecting traces is selected such that the total resistance of the one or more first connecting traces substantially matches the total resistance of the one or more second connecting traces.

5. The touch screen of claim 1, wherein one or more first connecting traces coupled to a first element are configured such that a total capacitance of the one or more first connecting traces substantially matches a total capacitance of one or more second connecting traces coupled to a second element.

6. The touch screen of claim 5, further comprising a trace extension coupled to each of the one or more first connecting traces, the trace extensions configured such that the total capacitance of the one or more first connecting traces substantially matches the total capacitance of the one or more second connecting traces.

7. The touch screen of claim 6, wherein a length of the trace extensions is selected such that the total capacitance of the one or more first connecting traces substantially matches the total capacitance of the one or more second connecting traces.

8. The touch screen of claim 6, wherein a width of the trace extensions is selected such that the total capacitance of the one or more first connecting traces substantially matches the total capacitance of the one or more second connecting traces.

9. The touch screen of claim 1:

wherein each of the plurality of elements are formed from a plurality of display pixel stackups; and

wherein the plurality of connecting traces are configured to equalize an effect of the connecting traces on the plurality of display pixel stackups.

10. The touch screen of claim 1, further comprising:

a data layer;

a gate layer; and

a connecting trace layer formed between the data layer and the gate layer;

wherein the plurality of connecting traces are formed in the connecting trace layer.

11. The touch screen of claim 1, wherein at least one of the plurality of connecting traces is routed under an opaque area of the display area.

12. The touch screen of claim 1, wherein at least one of the plurality of connecting traces is routed under a data line in the data layer.

13. A method of forming a touch screen comprising:

routing a plurality of elements formed in a display area of the touch screen to a second area using a plurality of connecting traces routed in the display area; and

forming the plurality of connecting traces to;

substantially balance a load created by the connecting traces, and

substantially not affect an aperture ratio of the touch screen.

14. The method of claim 13, further comprising matching a total resistance of one or more first connecting traces coupled to a first element with a total resistance of one or more second connecting traces coupled to a second element.

15. The method of claim 14, further comprising selecting a length of the one or more first connecting traces such that the total resistance of the one or more first connecting traces substantially matches the total resistance of the one or more second connecting traces.

16. The method of claim 14, further comprising selecting a width of the one or more first connecting traces such that the total resistance of the one or more first connecting traces substantially matches the total resistance of the one or more second connecting traces.

17. The method of claim 13, further comprising matching a total capacitance of one or more first connecting traces coupled to a first element with a total capacitance of one or more second connecting traces coupled to a second element.

18. The method of claim 17, further comprising extending each of the one or more first connecting traces such that the total capacitance of the one or more first connecting traces substantially matches the total capacitance of the one or more second connecting traces.

19. The method of claim 18, further comprising selecting a length of the trace extensions such that the total capacitance of the one or more first connecting traces substantially matches the total capacitance of the one or more second connecting traces.

20. The method of claim 18, further comprising selecting a width of the trace extensions such that the total capacitance of the one or more first connecting traces substantially matches the total capacitance of the one or more second connecting traces.

21. The method of claim 13, further comprising:

forming each of the plurality of elements from a plurality of display pixel stackups; and

forming the connecting traces to equalize an effect of the connecting traces on the plurality of display pixel stackups.

22. The method of claim 13, further comprising forming the plurality of connecting traces between a data layer and a gate layer.

23. The method of claim 13, further comprising routing at least one of the plurality of connecting traces under an opaque area of the display area.

24. The method of claim 13, further comprising routing at least one of the plurality of connecting traces under a data line in the data layer.