DATA CLOCK SYNCHRONIZATION IN HYBRID MEMORY MODULES

• US 20170200498A1
• Filed: 03/27/2017
• Published: 07/13/2017
• Est. Priority Date: 12/08/2015
• Status: Abandoned Application

• Current Assignee: Inphi Corporation
• Original Assignee: Inphi Corporation
• Inventors: SHALLAL, Aws, GIDDENS, Larry Grant
• Application Number:
  US15/470,650
• Publication Number:
  US 20170200498A1
• Time in Patent Office: Days
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 3/0611 in relation to response time
• CPC Class Codes: G06F 3/0655 Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices
• CPC Class Codes: G06F 3/0688 Non-volatile semiconductor memory arrays
• CPC Class Codes: G11C 11/005 comprising combined but independently operative RAM-ROM, RAM-PROM, RAM-EPROM cells
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 14/0018 whereby the nonvolatile element is an EEPROM element, e.g. a floating gate or metal-nitride-oxide-silicon [MNOS] transistor
• CPC Class Codes: G11C 16/32 Timing circuits
• CPC Class Codes: G11C 29/023 in clock generator or timing circuitry
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 5/04 Supports for storage elements , e.g. memory modules; Mounting or fixing of storage elements on such supports
• CPC Class Codes: G11C 7/08 Control thereof
• CPC Class Codes: G11C 7/10 Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
• CPC Class Codes: G11C 7/1057 Data output buffers, e.g. comprising level conversion circuits, circuits for adapting load
• CPC Class Codes: G11C 7/1066 Output synchronization
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1093 Input synchronization
• CPC Class Codes: G11C 7/222 Clock generating, synchronizing or distributing circuits within memory device

Abstract

Disclosed herein are techniques for implementing data clock synchronization in hybrid memory modules. Embodiments comprise a clock synchronization engine at a command buffer to generate a synchronized data clock having a phase relationship with data signals from a non-volatile memory controller that compensates for various synchronous and/or asynchronous delays to facilitate latching of the data signals at certain DRAM devices (e.g., during data restore operations). Other embodiments comprise a divider to determine the frequency of the synchronized data clock by dividing a local clock signal from the non-volatile memory controller by a selected divider value. Some embodiments comprise a set of synchronization logic that invokes the generation of the synchronized data clock signal responsive to receiving a certain local command and/or frame pulse from the non-volatile memory controller. In other embodiments, certain fixed and/or programmable delay elements can be implemented to compensate for various asynchronous delays.

Claims

1-20. -20. (canceled)

21. A system for performing backup and data restore operations between a volatile memory device and a non-volatile memory device, the system comprising:

one or more DRAM devices that are operatively connected through at least one data path to at least one non-volatile block-oriented mass storage device;

at least one non-volatile memory controller coupled to at least one of the DRAM devices to communicate one or more data signals to the DRAM devices;

a first circuit portion coupled to the non-volatile memory controller and the DRAM devices, to receive a local clock signal from the non-volatile memory controller; and

a second circuit portion to generate a synchronized data clock signal based at least in part on the local clock signal, wherein a first phase relationship between the synchronized data clock signal and the data signals facilitate latching of the data signals at the DRAM devices, and wherein the first phase relationship compensates for at least one of, one or more synchronous delays, or one or more asynchronous delays.

22. The system of claim 21, wherein the at least one non-volatile memory device is a flash memory device.

23. The system of claim 21, further comprising physical interface that is compliant with at least one of, a DDR4 memory, or an SDRAM memory.

24. The system of claim 21, further comprising a divider to determine a data clock signal frequency corresponding to the synchronized data clock signal based at least in part on a local clock signal frequency corresponding to the local clock signal.

25. The system of claim 24, wherein the data clock signal frequency is related to the local clock signal frequency by a divider value.

26. The system of claim 25, wherein the divider value is selectable from a plurality of available divider values.

27. The system of claim 26, wherein the available divider values comprise at least one of, 4, 2, or 1.

28. The system of claim 21, further comprising a set of synchronization logic to issue an alignment pulse to trigger the second circuit portion to generate the synchronized data clock signal.

29. The system of claim 28, wherein the alignment pulse is issued responsive to a local command received at the first circuit portion.

30. The system of claim 28, wherein the alignment pulse is issued a first quantity of local clock cycles associated with the local clock signal following a frame pulse received from the non-volatile memory controller.

31. The system of claim 21, further comprising a delay controller to select one or more programmable delay elements.

32. The system of claim 31, wherein the programmable delay elements are selected based at least in part the asynchronous delays.

33. The system of claim 21, further comprising a delay compensator to generate a phase delay characterizing a second phase relationship between the local clock signal and the data signals.

34. The system of claim 33, wherein the phase delay is generated by selecting one or more programmable delay elements.

35. The system of claim 21, further comprising one or more flash memory devices that are operatively connected to the at least one non-volatile memory controller.

36. The system of claim 21, wherein the data signals are latched at the DRAM devices in at least one burst.

37. The system of claim 21, wherein the synchronous delays comprise at least one of, a deterministic delay, a logic stage delay, or a flip-flop delay.

38. The system of claim 21, wherein the asynchronous delays comprise at least one of, a propagation delay, a gate delay, a buffer delay, or a printed circuit board trace delay.

39. The system of claim 21, wherein the at least one non-volatile block-oriented mass storage device is a solid state non-volatile memory device.

40. The system of claim 21, wherein the at least one non-volatile memory controller is packaged in a first package, and wherein the at least one non-volatile block-oriented mass storage device is packaged in a separate second package.