METHOD OF DETECTING ERASE FAIL WORD-LINE IN NON-VOLATILE MEMORY DEVICE

• US 20170200506A1
• Filed: 12/29/2016
• Published: 07/13/2017
• Est. Priority Date: 01/13/2016
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Original Assignee: Samsung Electronics Co. Ltd. (Samsung Group)
• Inventors: SHIM, Won-bo
• Granted Patent: US 9,704,596 B1
• Time in Patent Office: Days
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 11/108 Parity data distribution in semiconductor storages, e.g. in SSD
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/14 Circuits for erasing electrically, e.g. erase voltage switching circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/3445 Circuits or methods to verify correct erasure of nonvolatile memory cells
• CPC Class Codes: G11C 2029/0409 Online test
• CPC Class Codes: G11C 29/021 in voltage or current generators
• CPC Class Codes: G11C 29/025 in signal lines
• CPC Class Codes: G11C 29/028 with adaption or trimming of parameters
• CPC Class Codes: G11C 29/50004 of threshold voltage
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

A method for operating a non-volatile memory device initially includes supplying an erase voltage to the memory cells. The memory cells are in cell strings in a three-dimensional structure. The method further includes performing a first read operation of the memory cells, performing a second read operation of the memory cells, and then performing a first erase verify operation based on results of the first and second read operations. The first erase verify operation may include performing a first exclusive-or (XOR) operation on the first and second read operation results.

Claims

1. A method of operating a non-volatile memory device, including a plurality of cell strings, each of the cell strings including a plurality of memory cells, the method comprising:

supplying an erase voltage to the memory cells of each of the cell strings;

performing a first read operation by applying a first verify voltage to even word-lines connected to the memory cells of each of the cell strings and applying a high voltage to odd word-lines connected to the memory cells of each of the cell strings;

performing a second read operation by applying the first verify voltage to the odd word-lines connected to the memory cells of each of the cell strings and applying the high voltage to the even word-lines connected to the memory cells of each of the cell strings; and

performing a first erase verify operation by performing a first exclusive-or (XOR) operation on a result of the first read operation and a result of the second read operation.

2. The method as claimed in claim 1, wherein the first erase verify operation includes:

when a threshold voltage distribution of the memory cells connected to the even word-lines connected to the memory cells of each of the cell strings is different from a threshold voltage distribution of the memory cells connected to the odd word-lines connected to the memory cells of each of the cell strings when a voltage equal to or higher than the first verify voltage is applied, the first erase verify operation is processed as an erase fail.

3. The method as claimed in claim 1, wherein the first erase verify operation includes:

when a threshold voltage distribution of the memory cells connected to the even word-lines connected to the memory cells of each of the cell strings is same as a threshold voltage distribution of the memory cells connected to the odd word-lines connected to the memory cells of each of the cell strings when a voltage equal to or higher than the first verify voltage is applied, the first erase verify operation is processed as an erase pass.

4. The method as claimed in claim 1, wherein the first verify voltage is equal to an upper limit of a threshold voltage of erased memory cells.

5. The method as claimed in claim 1, wherein the high voltage is a non-selection read voltage supplied to non-selected word-lines during the first and second read operations.

6. The method as claimed in claim 1, wherein performing the first erase verify operation includes:

counting a number of first logic values as a result of the first XOR operation;

processing the first erase verify operation as an erase state fail when the number of first logic values is greater than correctable bits of an error correction unit, which corrects data errors of the non-volatile memory device; and

processing the first erase verify operation as an erase state pass when the number of first logic values is equal to or less than the correctable bits of the error correction unit.

7. The method as claimed in claim 1, further comprising, when the first erase verify operation is determined as an erase pass:

performing a third read operation by applying a second verify voltage different from the first verify voltage to the even word-lines connected to the memory cells of each of the cell strings, and applying the high voltage to the odd word-lines connected to the memory cells of each of the cell strings;

performing a fourth read operation by applying the second verify voltage to the odd word-lines connected to the memory cells of each of the cell strings and applying the high voltage to the even word-lines connected to the memory cells of each of the cell strings; and

performing a second erase verify operation by performing a second XOR operation on a result of the third read operation and a result of the fourth read operation.

8. The method as claimed in claim 7, wherein the second verify voltage is less than the first verify voltage.

9. The operation method as claimed in claim 7, wherein performing the second erase verify operation includes:

counting a number of first logic values as a result of the second XOR operation;

processing the second erase verify operation as an erase state fail and ending an erase operation when the number of first logic values is greater than correctable bits of an error correction unit; and

processing the second erase verify operation as an erase state pass and ending the erase operation when the number of first logic values is equal to or less than the correctable bits of the error correction unit.

10. A method of operating a non-volatile memory device, including a plurality of cell strings on a substrate, each of the cell strings including a plurality of memory cells stacked in a direction perpendicular to the substrate, the method comprising:

supplying an erase voltage to the memory cells of each of the cell strings;

performing a first erase verify operation by applying a high voltage to word-lines connected to the memory cells of each of the cell strings;

with respect to the cell strings determined as an erase pass, as a result of the first erase verify operation, performing a first read operation by applying a first verify voltage to even word-lines of the word-lines connected to the memory cells and applying the high voltage to odd word-lines of the word-lines connected to the memory cells;

performing a second read operation by applying the first verify voltage to the odd word-lines of the word-lines connected to the memory cells and applying the high voltage to the even word-lines of the word-lines connected to the memory cells; and

performing a second erase verify operation by performing a first exclusive-or (XOR) operation on a result of the first read operation and a result of the second read operation.

11. The method as claimed in claim 10, wherein:

when the first erase verify operation is determined as an erase fail, the first erase verify operation is processed as an erase state fail and an erase operation is ended.

12. The operation method as claimed in claim 10, wherein the second erase verify operation includes:

when a threshold voltage distribution of the memory cells connected to the even word-lines of the word-lines connected to the memory cells is different from a threshold voltage distribution of the memory cells connected to the odd word-lines of the word-lines connected to the memory cells when a voltage equal to or higher than the first verify voltage is applied, the second erase verify operation is processed as an erase fail.

13. The method as claimed in claim 10, wherein the second erase verify operation includes:

when a threshold voltage distribution of the memory cells connected to the even word-lines of the word-lines connected to the memory cells is same as a threshold voltage distribution of the memory cells connected to the odd word-lines of the word-lines connected to the memory cells when a voltage equal to or higher than the first verify voltage is applied, the second erase verify operation is processed as an erase pass.

14. The method as claimed in claim 10, further comprising:

with respect to the cell strings determined as an erase pass as a result of the second erase verify operation, performing a third read operation by applying a second verify voltage different from the first verify voltage to the even word-lines of the word-lines connected to the memory cells and applying the high voltage to the odd word-lines of the word-lines connected to the memory cells;

performing a fourth read operation by applying the second verify voltage to the odd word-lines of the word-lines connected to the memory cells and applying the high voltage to the even word-lines of the word-lines connected to the memory cells; and

performing the second erase verify operation by performing a second XOR operation on a result of the third read operation and a result of the fourth read operation.

15. The method as claimed in claim 14, wherein the second verify voltage is less than the first verify voltage.

16. A method for controlling a non-volatile memory, the method comprising:

performing a first read operation including applying a first voltage to a first number of word lines connected to a plurality of memory cells, and applying a second voltage to a second number of word lines connected to the memory cells;

performing a second read operation including applying the first voltage to the second number of word lines, and applying the second voltage to the first number of word lines; and

detecting an erase fail word-line based on results of the first and second read operations, wherein the first voltage is different from the second voltage.

17. The method as claimed in claim 16, wherein:

the first number of word lines are even word lines, and

the second number of word lines are odd word lines.

18. The method as claimed in claim 16, wherein detecting the erase fail word-line includes comparing the results of the first read operation to the results of the second read operation.

19. The method as claimed in claim 18, wherein the comparing includes:

performing an exclusive-or operation on the results of the first and second read operations.

20. The method as claimed in claim 16, wherein:

the non-volatile memory has a three-dimensional structure, and

the memory cells are arranged in different cell strings of the three-dimensional structure.