LOW WARPAGE WAFER BONDING THROUGH USE OF SLOTTED SUBSTRATES

• US 20170200853A1
• Filed: 02/21/2017
• Published: 07/13/2017
• Est. Priority Date: 10/21/2011
• Status: Active Grant

• Current Assignee: Lumileds LLC (Apollo Global Management, Inc.)
• Original Assignee: Koninklijke Philips N.V.
• Inventors: De Samber, Marc Andre, Van Grunsven, Eric Cornelis Egbertus, Engelen, Roy Antoin Bastiaan
• Granted Patent: US 10,084,110 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 21/2007 Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer H01L21/2011 takes precedence; bonding of semiconductor wafers to semiconductor wafers for junction formation H01L21/187
• CPC Class Codes: H01L 25/0753 the devices being arranged next to each other
• CPC Class Codes: H01L 2933/0066 relating to arrangements for conducting electric current to or from the semiconductor body
• CPC Class Codes: H01L 33/0054 for devices with an active region comprising only group IV elements
• CPC Class Codes: H01L 33/0093 Wafer bonding; Removal of the growth substrate
• CPC Class Codes: H01L 33/0095 Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
• CPC Class Codes: H01L 33/12 with a stress relaxation structure, e.g. buffer layer
• CPC Class Codes: H01L 33/486 adapted for surface mounting
• CPC Class Codes: H01L 33/62 Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls

Abstract

In a wafer bonding process, one or both of two wafer substrates are scored prior to bonding. By creating slots in the substrate, the wafer'"'"'s characteristics during bonding are similar to that of a thinner wafer, thereby reducing potential warpage due to differences in CTE characteristics associated with each of the wafers. Preferably, the slots are created consistent with the singulation/dicing pattern, so that the slots will not be present in the singulated packages, thereby retaining the structural characteristics of the full-thickness substrates.

Claims

1. A method comprising:

providing a first wafer comprising a plurality of light emitting semiconductor devices grown on a growth substrate;

providing a second wafer comprising a first surface, a second surface opposite the first surface, and a plurality of slots formed on the second surface;

aligning the plurality of slots with boundaries between light emitting semiconductor devices on the first wafer; and

bonding the first surface of the second wafer to the first wafer.

2. The method of claim 1 further comprising after bonding the first surface of the second wafer to the first wafer, removing the growth substrate.

3. The method of claim 1 wherein the growth substrate is sapphire and the second wafer is silicon.

4. The method of claim 1 wherein the second wafer has a thickness T, and the slots have a depth D that is between forty and eighty percent of the thickness T.

5. The method of claim 1 wherein the light emitting semiconductor devices have a device width, and the slots have a slot width that is between five and twenty percent of the device width.

6. The method of claim 1 further comprising forming in the second wafer a plurality of through-holes aligned with contact areas on the light emitting semiconductor devices, the through-holes extending through an entire thickness of the second wafer.

7. The method of claim 1 wherein neighboring slots are disposed an integer number of light emitting semiconductor devices apart.

8. A method comprising:

providing a first wafer comprising a plurality of light emitting semiconductor devices grown on a growth substrate;

providing a second wafer comprising a first surface, a second surface opposite the first surface, and a plurality of slots formed on the second surface;

bonding the first surface of the second wafer to the first wafer; and

after bonding the first surface of the second wafer to the first wafer, removing the growth substrate.

9. The method of claim 8 wherein the growth substrate is sapphire and the second wafer is silicon.

10. The method of claim 8 further comprising forming in the second wafer a plurality of through-holes aligned with contact areas on the light emitting semiconductor devices, the through-holes extending through an entire thickness of the second wafer.

11. The method of claim 10 further comprising disposing conductors in the through-holes.

12. The method of claim 8 further comprising, after removing the growth substrate, dicing the first and second wafers into individual light emitting semiconductor devices or groups of light emitting semiconductor devices.

13. A method comprising:

determining a thickness of a submount wafer;

determining a maximum allowable warpage of a wafer of light emitting semiconductor devices;

determining a maximum effective thickness of the submount wafer, based on the maximum allowable warpage of the wafer of light emitting semiconductor devices;

comparing the thickness of the submount wafer to the maximum effective thickness of the submount wafer; and

if the thickness of the submount wafer is greater than the maximum effective thickness of the submount wafer, determining a pitch, depth, and width of a plurality of slots to be formed in the submount wafer.

14. The method of claim 13 further comprising forming a plurality of slots in the submount wafer.

15. The method of claim 14 further comprising bonding the submount wafer to the wafer of light emitting semiconductor devices.

16. The method of claim 13 wherein determining a thickness of a submount wafer comprises determining the thickness of the submount wafer based on structural support required for the wafer of light emitting semiconductor devices during fabrication or post-fabrication processes.

17. The method of claim 13 wherein determining a maximum effective thickness of the submount wafer comprises determining a maximum effective thickness of the submount wafer based on an expected bonding temperature of the submount wafer and the wafer of light emitting semiconductor devices.