ALL-DIGITAL PHASE LOCKED LOOP (ADPLL) INCLUDING A DIGITAL-TO-TIME CONVERTER (DTC) AND A SAMPLING TIME-TO-DIGITAL CONVERTER (TDC)
First Claim
1. A digital phase locked loop (DPLL) circuit comprising:
- a digital-to-time converter (DTC) configured to generate a delayed reference clock signal by delaying a reference clock signal according to a delay control signal; and
a time-to-digital converter (TDC) coupled to an output of the DTC, the TDC being configured to sample a value of a transition signal according to the delayed reference clock signal and to generate an output signal indicating a phase difference between the delayed clock signal and an input clock signal, the transition signal transitioning between a logic high value and a logic low value.
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Abstract
A digital phase locked loop (DPLL) circuit includes a digital-to-time converter (DTC) configured to generate a delayed reference clock signal by delaying a reference clock signal according to a delay control signal and a time-to-digital converter (TDC) coupled to an output of the DTC. The TDC is configured to sample a value of a transition signal according to the delayed reference clock signal and to generate an output signal indicating a phase difference between the delayed clock signal and an input clock signal. A method of controlling a DPLL includes delaying a reference clock signal according to a delay control signal, sampling a value of a transition signal according to the delayed reference clock signal, generating an output signal indicating a phase difference between the delayed clock signal and an input clock signal, and generating a digitally controlled oscillator (DCO) clock signal according to the output signal.
32 Citations
20 Claims
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1. A digital phase locked loop (DPLL) circuit comprising:
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a digital-to-time converter (DTC) configured to generate a delayed reference clock signal by delaying a reference clock signal according to a delay control signal; and a time-to-digital converter (TDC) coupled to an output of the DTC, the TDC being configured to sample a value of a transition signal according to the delayed reference clock signal and to generate an output signal indicating a phase difference between the delayed clock signal and an input clock signal, the transition signal transitioning between a logic high value and a logic low value. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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14. A method of controlling a digital phase locked loop (DPLL) comprising
delaying a reference clock signal according to a delay control signal; -
sampling a value of a transition signal according to the delayed reference clock signal and generating an output signal indicating a phase difference between the delayed clock signal and an input clock signal, the transition signal transitioning between a logic high value and a logic low value; and generating a digitally controlled oscillator (DCO) clock signal according to the output signal. - View Dependent Claims (15, 16, 17, 18, 19, 20)
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Specification