SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE

• US 20170207347A1
• Filed: 01/18/2017
• Published: 07/20/2017
• Est. Priority Date: 01/20/2016
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: ENDO, Yuta, SUZAWA, Hideomi, HANAOKA, Kazuya, SASAGAWA, Shinya, OKAMOTO, Satoru
• Granted Patent: US 9,905,657 B2
• Time in Patent Office: Days
• CPC Class Codes: H01L 2029/42388 characterised by the shape of the insulating material
• CPC Class Codes: H01L 21/8258 the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/1211 combined with field-effect transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 27/14616 characterised by the channel of the transistor, e.g. channel having a doping gradient
• CPC Class Codes: H01L 29/401 Multistep manufacturing processes
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/41791 for transistors with a horizontal current flow in a vertical sidewall, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66969 of devices having semiconductor bodies not comprising group 14 or group 13/15 materials comprising selenium or tellurium in uncombined form other than as impurities in semiconductor bodies of other materials, comprising cuprous oxide or cuprous iodide H01L21/02365
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/78648 arranged on opposing sides of the channel
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78693 the semiconducting oxide being amorphous
• CPC Class Codes: H01L 29/78696 : characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621

Abstract

A semiconductor device in which parasitic capacitance is reduced is provided. A first oxide insulating layer and a first oxide semiconductor layer are sequentially formed over a first insulating layer. A first conductive layer is formed over the first oxide semiconductor layer and etched to form a second conductive layer. The first oxide insulating layer and the first oxide semiconductor layer are etched with the second conductive layer as a mask to form a second oxide insulating layer and a second oxide semiconductor layer. A planarized insulating layer is formed over the first insulating layer and the second conductive layer. A second insulating layer, a source electrode layer, and a drain electrode layer are formed by etching the planarized insulating layer and the second conductive layer. A third oxide insulating layer, a gate insulating layer, and a gate electrode layer are formed over the second oxide semiconductor layer.

Claims

1. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first insulating layer over a substrate;

forming a first oxide insulating layer over the first insulating layer;

forming a first oxide semiconductor layer over the first oxide insulating layer;

forming a second insulating layer over the first oxide semiconductor layer;

forming a third insulating layer by etching the second insulating layer with a first mask so that a first part of the first oxide semiconductor layer is exposed;

forming a first conductive layer over the first oxide semiconductor layer and the third insulating layer;

forming a second conductive layer by performing etch-back treatment on the first conductive layer so that a second part of the first oxide semiconductor layer is exposed, wherein the second conductive layer comprises a region in contact with a side surface of the third insulating layer;

removing the third insulating layer;

forming a second oxide insulating layer and a second oxide semiconductor layer by etching the first oxide insulating layer and the first oxide semiconductor layer with the second conductive layer as a second mask so that the first insulating layer is exposed;

forming a fourth insulating layer over the first insulating layer and the second conductive layer;

forming a fifth insulating layer by performing planarization treatment on the fourth insulating layer;

forming a sixth insulating layer, a source electrode layer, and a drain electrode layer by etching the fifth insulating layer and the second conductive layer with a third mask;

forming a third oxide insulating layer, a seventh insulating layer, and a third conductive layer over the sixth insulating layer and the second oxide semiconductor layer; and

forming a fourth oxide insulating layer, a gate insulating layer, and a gate electrode layer by performing planarization treatment on the third oxide insulating layer, the seventh insulating layer, and the third conductive layer.

2. The method for manufacturing a semiconductor device according to claim 1, wherein the first conductive layer is formed by a CVD method.

3. The method for manufacturing a semiconductor device according to claim 1, wherein the first conductive layer comprises at least one of aluminum, titanium, cobalt, nickel, copper, molybdenum, ruthenium, silver, tantalum, tungsten, platinum, palladium, silicon, iridium, iron, manganese, nitrogen, and oxygen.

4. The method for manufacturing a semiconductor device according to claim 1, wherein an angle between the side surface of the third insulating layer and a top surface of the substrate is substantially perpendicular.

5. The method for manufacturing a semiconductor device according to claim 1, wherein a thickness of the first conductive layer is greater than or equal to 4 nm and less than or equal to 40 nm.

6. A method for manufacturing a semiconductor device, comprising the steps of:

forming a first insulating layer over a substrate;

forming a first oxide insulating layer over the first insulating layer;

forming a first oxide semiconductor layer over the first oxide insulating layer;

forming a second insulating layer over the first oxide semiconductor layer;

forming a third insulating layer by etching the second insulating layer with a first mask, wherein the third insulating layer has a frame shape when seen from a direction perpendicular to a surface of the substrate;

forming a first conductive layer over the first oxide semiconductor layer and the third insulating layer;

forming a second conductive layer by performing etch-back treatment on the first conductive layer, wherein the second conductive layer comprises a region in contact with inside and outside surfaces of a frame of the third insulating layer;

removing the third insulating layer;

forming a third conductive layer by etching the second conductive layer with a second mask, wherein the third conductive layer has a rectangular shape when seen from the direction perpendicular to the surface of the substrate;

forming a second oxide insulating layer and a second oxide semiconductor layer by etching the first oxide insulating layer and the first oxide semiconductor layer with the third conductive layer as a third mask;

forming a fourth insulating layer over the first insulating layer and the third conductive layer;

forming a fifth insulating layer by performing planarization treatment on the fourth insulating layer;

forming a sixth insulating layer, a source electrode layer, and a drain electrode layer by etching the fifth insulating layer and the third conductive layer with a fourth mask;

forming a third oxide insulating layer over the sixth insulating layer and the second oxide semiconductor layer;

forming a seventh insulating layer over the third oxide insulating layer;

forming a fourth conductive layer over the seventh insulating layer; and

forming a fourth oxide insulating layer, a gate insulating layer, and a gate electrode layer by performing planarization treatment on the third oxide insulating layer, the seventh insulating layer, and the fourth conductive layer.

7. The method for manufacturing a semiconductor device according to claim 6, wherein the first conductive layer is formed by a CVD method.

8. The method for manufacturing a semiconductor device according to claim 6, wherein the first conductive layer comprises at least one of aluminum, titanium, cobalt, nickel, copper, molybdenum, ruthenium, silver, tantalum, tungsten, platinum, palladium, silicon, iridium, iron, manganese, nitrogen, and oxygen.

9. The method for manufacturing a semiconductor device according to claim 6, wherein an angle between a side surface of the third insulating layer and a top surface of the substrate is substantially perpendicular.

10. The method for manufacturing a semiconductor device according to claim 6, wherein a thickness of the first conductive layer is greater than or equal to 4 nm and less than or equal to 40 nm.

11. A semiconductor device comprising:

a first oxide insulating layer over a first insulating layer;

an oxide semiconductor layer over the first oxide insulating layer;

a second oxide insulating layer over the oxide semiconductor layer;

a gate insulating layer over the second oxide insulating layer;

a gate electrode layer over the gate insulating layer; and

a second insulating layer over the oxide semiconductor layer,

wherein, in a cross section in a channel width direction, a ratio of a length of a bottom surface of the oxide semiconductor layer in the channel width direction to a length of a central portion of the oxide semiconductor layer in a thickness direction is less than or equal to 2.

12. The semiconductor device according to claim 11, wherein a length of the oxide semiconductor layer in the channel width direction is less than or equal to 30 nm.

13. The semiconductor device according to claim 11, wherein at least one of corners of the oxide semiconductor layer is rounded.